arm: bcmbca: add bcm63178 SoC support

BCM63178 is an ARM A7 based DSL Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and ARM PL011 uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux with minor fix-up that needs to be
upstreamed to linux as well.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 048db37cb4d07083a2c1aa37439ea48df89b4d2f..b73f2d0ce658aec0fe80db04a0708287671224f4 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -216,8 +216,9 @@ M:  Joel Peshkin <joel.peshkin@broadcom.com>
 S:     Maintained
 F:     arch/arm/mach-bcmbca/
 F:     board/broadcom/bcmbca/
-F:     configs/bcm947622_defconfig
-F:     include/configs/bcm947622.h
+N:     bcmbca
+N:     bcm[9]?47622
+N:     bcm[9]?63178
 
 ARM BROADCOM BCMSTB
 M:     Thomas Fitzsimmons <fitzsim@fitzsim.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5c7cdc9847b35a13cddc4d25c672b5071cfe1c2e..6c70d128087d4f74349cc89bb703ce8f93ac5cc4 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1182,6 +1182,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
 
 dtb-$(CONFIG_BCM47622) += \
        bcm947622.dtb
+dtb-$(CONFIG_BCM63178) += \
+       bcm963178.dtb
 
 dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
 dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb

diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi
new file mode 100644 (file)
index 0000000..cbd094d
--- /dev/null
+++ b/arch/arm/dts/bcm63178.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       compatible = "brcm,bcm63178", "brcm,bcmbca";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               CA7_0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x0>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               CA7_1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x1>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               CA7_2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x2>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+               arm,cpu-registers-not-fw-configured;
+       };
+
+       pmu: pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&CA7_0>, <&CA7_1>,
+                       <&CA7_2>;
+       };
+
+       clocks: clocks {
+               periph_clk: periph-clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
+               uart_clk: uart-clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clocks = <&periph_clk>;
+                       clock-div = <4>;
+                       clock-mult = <1>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       axi@81000000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x81000000 0x8000>;
+
+               gic: interrupt-controller@1000 {
+                       compatible = "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+                       reg = <0x1000 0x1000>,
+                               <0x2000 0x2000>,
+                               <0x4000 0x2000>,
+                               <0x6000 0x2000>;
+               };
+       };
+
+       bus@ff800000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xff800000 0x800000>;
+
+               uart0: serial@12000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0x12000 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&uart_clk>, <&uart_clk>;
+                       clock-names = "uartclk", "apb_pclk";
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts
new file mode 100644 (file)
index 0000000..fa096e9
--- /dev/null
+++ b/arch/arm/dts/bcm963178.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63178.dtsi"
+
+/ {
+       model = "Broadcom BCM963178 Reference Board";
+       compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x08000000>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
index 2d49380f879b7bf96196eba2fbf3c518be297415..99e26e4ab8c9688641eeb38e3a9a0c0062560955 100644 (file)
--- a/arch/arm/mach-bcmbca/Kconfig
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -12,6 +12,14 @@ config BCM47622
        select DM_SERIAL
        select PL01X_SERIAL
 
-endif
+config BCM63178
+       bool "Support for Broadcom 63178 Family"
+       select SYS_ARCH_TIMER
+       select CPU_V7A
+       select DM_SERIAL
+       select PL01X_SERIAL
 
 source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
+
+endif

diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
index 072d4ea7b5e606f98b6875a2d4c5c4edd448d194..fdcade6bfe1ac583c76f5edfd3ff9e0ea4b60619 100644 (file)
--- a/arch/arm/mach-bcmbca/Makefile
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_BCM47622) += bcm47622/
+obj-$(CONFIG_BCM63178) += bcm63178/

diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig
new file mode 100644 (file)
index 0000000..73ac462
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63178
+
+config TARGET_BCM963178
+       bool "Broadcom 63178 Reference Board"
+       depends on ARCH_BCMBCA
+
+config SYS_SOC
+       default "bcm63178"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif

diff --git a/arch/arm/mach-bcmbca/bcm63178/Makefile b/arch/arm/mach-bcmbca/bcm63178/Makefile
new file mode 100644 (file)
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o

diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
index 63d4252da620c87d7ec8c12034589a456ef6efc1..53846761b664906249d8d2dab467119bdb91d005 100644 (file)
--- a/board/broadcom/bcmbca/Kconfig
+++ b/board/broadcom/bcmbca/Kconfig
@@ -15,3 +15,10 @@ config SYS_CONFIG_NAME
        default "bcm947622"
 
 endif
+
+if TARGET_BCM963178
+
+config SYS_CONFIG_NAME
+       default "bcm963178"
+
+endif

diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig
new file mode 100644 (file)
index 0000000..d9e62cf
--- /dev/null
+++ b/configs/bcm963178_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63178=y
+CONFIG_TARGET_BCM963178=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
+CONFIG_IDENT_STRING=" Broadcom BCM63178"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y

diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h
new file mode 100644 (file)
index 0000000..b25f6a1
--- /dev/null
+++ b/include/configs/bcm963178.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963178_H
+#define __BCM963178_H
+
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+
+#endif