fix(cpus): update doc and check for plat_can_cmo

plat_can_cmo must not clobber x1 but the doc doesn't mention that. This
patch updates the doc to mention x1. It also adds check for plat_can_cmo
to `dcsw_op_louis` which was missed out in original patch.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I721376bf3726520d0d5b0df0f33f98ce92257287

diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 7f38054940df8c345f006fe40bbbffbf4b88bb66..aa57e1db6be645ef325f636a9e4d02df0331a3ac 100644 (file)
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1502,8 +1502,8 @@ When CONDITIONAL_CMO flag is enabled:
 - This function indicates whether cache management operations should be
   performed. It returns 0 if CMOs should be skipped and non-zero
   otherwise.
-- The function must not clobber x2 and x3. It's also not safe to rely on stack.
-  Otherwise obey AAPCS.
+- The function must not clobber x1, x2 and x3. It's also not safe to rely on
+  stack. Otherwise obey AAPCS.
 
 Modifications specific to a Boot Loader stage
 ---------------------------------------------

diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S
index 67fafb1e7a07b78c28b836733f77ed337fda42ca..314ed6efd7d04c84195df588be1361433f56c0e3 100644 (file)
--- a/lib/aarch64/cache_helpers.S
+++ b/lib/aarch64/cache_helpers.S
@@ -217,6 +217,7 @@ dcsw_loop_table:
 
 
 func dcsw_op_louis
+       check_plat_can_cmo
        dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
 endfunc dcsw_op_louis