drm/i915: rename CNL references in intel_dram.c

With the removal of CNL, let's consider ICL as the first platform using
those constants.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-21-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11a30b1ac030a139d7709e2d88893ab51a138917..30669ae4b8c47ea4683cc2de9c69713f6fd8c659 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11152,18 +11152,18 @@ enum skl_power_gate {
 #define  SKL_DRAM_RANK_1                       (0x0 << 10)
 #define  SKL_DRAM_RANK_2                       (0x1 << 10)
 #define  SKL_DRAM_RANK_MASK                    (0x1 << 10)
-#define  CNL_DRAM_SIZE_MASK                    0x7F
-#define  CNL_DRAM_WIDTH_MASK                   (0x3 << 7)
-#define  CNL_DRAM_WIDTH_SHIFT                  7
-#define  CNL_DRAM_WIDTH_X8                     (0x0 << 7)
-#define  CNL_DRAM_WIDTH_X16                    (0x1 << 7)
-#define  CNL_DRAM_WIDTH_X32                    (0x2 << 7)
-#define  CNL_DRAM_RANK_MASK                    (0x3 << 9)
-#define  CNL_DRAM_RANK_SHIFT                   9
-#define  CNL_DRAM_RANK_1                       (0x0 << 9)
-#define  CNL_DRAM_RANK_2                       (0x1 << 9)
-#define  CNL_DRAM_RANK_3                       (0x2 << 9)
-#define  CNL_DRAM_RANK_4                       (0x3 << 9)
+#define  ICL_DRAM_SIZE_MASK                    0x7F
+#define  ICL_DRAM_WIDTH_MASK                   (0x3 << 7)
+#define  ICL_DRAM_WIDTH_SHIFT                  7
+#define  ICL_DRAM_WIDTH_X8                     (0x0 << 7)
+#define  ICL_DRAM_WIDTH_X16                    (0x1 << 7)
+#define  ICL_DRAM_WIDTH_X32                    (0x2 << 7)
+#define  ICL_DRAM_RANK_MASK                    (0x3 << 9)
+#define  ICL_DRAM_RANK_SHIFT                   9
+#define  ICL_DRAM_RANK_1                       (0x0 << 9)
+#define  ICL_DRAM_RANK_2                       (0x1 << 9)
+#define  ICL_DRAM_RANK_3                       (0x2 << 9)
+#define  ICL_DRAM_RANK_4                       (0x3 << 9)
 
 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC         _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
 #define  DG1_QCLK_RATIO_MASK                   REG_GENMASK(9, 2)

diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 83924732183d3262294dbb514f56c8f8046a9e74..91866520c173a473d153765305687c637e9457ed 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
 }
 
 /* Returns total Gb for the whole DIMM */
-static int cnl_get_dimm_size(u16 val)
+static int icl_get_dimm_size(u16 val)
 {
-       return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
+       return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
 }
 
-static int cnl_get_dimm_width(u16 val)
+static int icl_get_dimm_width(u16 val)
 {
-       if (cnl_get_dimm_size(val) == 0)
+       if (icl_get_dimm_size(val) == 0)
                return 0;
 
-       switch (val & CNL_DRAM_WIDTH_MASK) {
-       case CNL_DRAM_WIDTH_X8:
-       case CNL_DRAM_WIDTH_X16:
-       case CNL_DRAM_WIDTH_X32:
-               val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
+       switch (val & ICL_DRAM_WIDTH_MASK) {
+       case ICL_DRAM_WIDTH_X8:
+       case ICL_DRAM_WIDTH_X16:
+       case ICL_DRAM_WIDTH_X32:
+               val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
                return 8 << val;
        default:
                MISSING_CASE(val);
@@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
        }
 }
 
-static int cnl_get_dimm_ranks(u16 val)
+static int icl_get_dimm_ranks(u16 val)
 {
-       if (cnl_get_dimm_size(val) == 0)
+       if (icl_get_dimm_size(val) == 0)
                return 0;
 
-       val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
+       val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
 
        return val + 1;
 }
@@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
                       struct dram_dimm_info *dimm,
                       int channel, char dimm_name, u16 val)
 {
-       if (GRAPHICS_VER(i915) >= 10) {
-               dimm->size = cnl_get_dimm_size(val);
-               dimm->width = cnl_get_dimm_width(val);
-               dimm->ranks = cnl_get_dimm_ranks(val);
+       if (GRAPHICS_VER(i915) >= 11) {
+               dimm->size = icl_get_dimm_size(val);
+               dimm->width = icl_get_dimm_width(val);
+               dimm->ranks = icl_get_dimm_ranks(val);
        } else {
                dimm->size = skl_get_dimm_size(val);
                dimm->width = skl_get_dimm_width(val);