board: verdin-imx8mp: update lpddr4 configuration and training

Update LPDDR4 configuration and training using updated spreadsheet and
tools from NXP using data from previous spreadsheet and verified
toward datasheet:
 - MX8M_Plus_LPDDR4_RPA_v9.xlsx
 - mscale_ddr_tool_v3.30.exe

From:
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467

Some register values differ due to these fixes/modifications:

- corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4)
- corrected ECC related items, none of which affect normal operation
  when ECC is not enabled
- corrected formula for calculation of tRTP in cell D122

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 58278d2150a9ca0f88a413d04b578719000c46d6..4f0bbe6ce16d9bd0d23cb4279fb8f810f66c1613 100644 (file)
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -22,8 +22,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400020, 0x1303 },
        { 0x3d400024, 0x1e84800 },
        { 0x3d400064, 0x7a017c },
-       { 0x3d400070, 0x61027f10 },
-       { 0x3d400074, 0x7b0 },
+       { 0x3d400070, 0x7027f90 },
+       { 0x3d400074, 0x790 },
        { 0x3d4000d0, 0xc00307a3 },
        { 0x3d4000d4, 0xc50000 },
        { 0x3d4000dc, 0xf4003f },
@@ -31,12 +31,12 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4000e8, 0x660048 },
        { 0x3d4000ec, 0x160048 },
        { 0x3d400100, 0x2028222a },
-       { 0x3d400104, 0x807bf },
+       { 0x3d400104, 0x8083f },
        { 0x3d40010c, 0xe0e000 },
        { 0x3d400110, 0x12040a12 },
        { 0x3d400114, 0x2050f0f },
        { 0x3d400118, 0x1010009 },
-       { 0x3d40011c, 0x501 },
+       { 0x3d40011c, 0x502 },
        { 0x3d400130, 0x20800 },
        { 0x3d400134, 0xe100002 },
        { 0x3d400138, 0x184 },
@@ -53,9 +53,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4001b0, 0x11 },
        { 0x3d4001c0, 0x1 },
        { 0x3d4001c4, 0x1 },
-       { 0x3d4000f4, 0xc99 },
-       { 0x3d400108, 0x9121c1c },
+       { 0x3d4000f4, 0x799 },
+       { 0x3d400108, 0x9121b1c },
        { 0x3d400200, 0x17 },
+       { 0x3d400208, 0x0 },
        { 0x3d40020c, 0x0 },
        { 0x3d400210, 0x1f1f },
        { 0x3d400204, 0x80808 },
@@ -89,7 +90,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402110, 0x2040202 },
        { 0x3d402114, 0x2030202 },
        { 0x3d402118, 0x1010004 },
-       { 0x3d40211c, 0x301 },
+       { 0x3d40211c, 0x302 },
        { 0x3d402130, 0x20300 },
        { 0x3d402134, 0xa100002 },
        { 0x3d402138, 0x27 },
@@ -98,7 +99,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402190, 0x3818200 },
        { 0x3d402194, 0x80303 },
        { 0x3d4021b4, 0x100 },
-       { 0x3d4020f4, 0xc99 },
+       { 0x3d4020f4, 0x599 },
        { 0x3d403020, 0x1001 },
        { 0x3d403024, 0xc3500 },
        { 0x3d403050, 0x20d000 },
@@ -114,7 +115,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403110, 0x2040202 },
        { 0x3d403114, 0x2030202 },
        { 0x3d403118, 0x1010004 },
-       { 0x3d40311c, 0x301 },
+       { 0x3d40311c, 0x302 },
        { 0x3d403130, 0x20300 },
        { 0x3d403134, 0xa100002 },
        { 0x3d403138, 0xa },
@@ -123,7 +124,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403190, 0x3818200 },
        { 0x3d403194, 0x80303 },
        { 0x3d4031b4, 0x100 },
-       { 0x3d4030f4, 0xc99 },
+       { 0x3d4030f4, 0x599 },
        { 0x3d400028, 0x0 },
 };
 
@@ -1700,15 +1701,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
        { 0x200be, 0x3 },
-       { 0x2000b, 0x7d },
+       { 0x2000b, 0x465 },
        { 0x2000c, 0xfa },
        { 0x2000d, 0x9c4 },
        { 0x2000e, 0x2c },
-       { 0x12000b, 0xc },
+       { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
        { 0x12000d, 0xfa },
        { 0x12000e, 0x10 },
-       { 0x22000b, 0x3 },
+       { 0x22000b, 0x1c },
        { 0x22000c, 0x6 },
        { 0x22000d, 0x3e },
        { 0x22000e, 0x10 },
@@ -1842,8 +1843,8 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d400020, 0x1303 },
        { 0x3d400024, 0x1e84800 },
        { 0x3d400064, 0x7a017c },
-       { 0x3d400070, 0x61027f10 },
-       { 0x3d400074, 0x7b0 },
+       { 0x3d400070, 0x7027f90 },
+       { 0x3d400074, 0x790 },
        { 0x3d4000d0, 0xc00307a3 },
        { 0x3d4000d4, 0xc50000 },
        { 0x3d4000dc, 0xf4003f },
@@ -1851,12 +1852,12 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d4000e8, 0x660048 },
        { 0x3d4000ec, 0x160048 },
        { 0x3d400100, 0x2028222a },
-       { 0x3d400104, 0x807bf },
+       { 0x3d400104, 0x8083f },
        { 0x3d40010c, 0xe0e000 },
        { 0x3d400110, 0x12040a12 },
        { 0x3d400114, 0x2050f0f },
        { 0x3d400118, 0x1010009 },
-       { 0x3d40011c, 0x501 },
+       { 0x3d40011c, 0x502 },
        { 0x3d400130, 0x20800 },
        { 0x3d400134, 0xe100002 },
        { 0x3d400138, 0x184 },
@@ -1873,9 +1874,10 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d4001b0, 0x11 },
        { 0x3d4001c0, 0x1 },
        { 0x3d4001c4, 0x1 },
-       { 0x3d4000f4, 0xc99 },
-       { 0x3d400108, 0x9121c1c },
+       { 0x3d4000f4, 0x799 },
+       { 0x3d400108, 0x9121b1c },
        { 0x3d400200, 0x1f },
+       { 0x3d400208, 0x0 },
        { 0x3d40020c, 0x0 },
        { 0x3d400210, 0x1f1f },
        { 0x3d400204, 0x80808 },
@@ -1909,7 +1911,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d402110, 0x2040202 },
        { 0x3d402114, 0x2030202 },
        { 0x3d402118, 0x1010004 },
-       { 0x3d40211c, 0x301 },
+       { 0x3d40211c, 0x302 },
        { 0x3d402130, 0x20300 },
        { 0x3d402134, 0xa100002 },
        { 0x3d402138, 0x27 },
@@ -1918,7 +1920,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d402190, 0x3818200 },
        { 0x3d402194, 0x80303 },
        { 0x3d4021b4, 0x100 },
-       { 0x3d4020f4, 0xc99 },
+       { 0x3d4020f4, 0x599 },
        { 0x3d403020, 0x1001 },
        { 0x3d403024, 0xc3500 },
        { 0x3d403050, 0x20d000 },
@@ -1934,7 +1936,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d403110, 0x2040202 },
        { 0x3d403114, 0x2030202 },
        { 0x3d403118, 0x1010004 },
-       { 0x3d40311c, 0x301 },
+       { 0x3d40311c, 0x302 },
        { 0x3d403130, 0x20300 },
        { 0x3d403134, 0xa100002 },
        { 0x3d403138, 0xa },
@@ -1943,7 +1945,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
        { 0x3d403190, 0x3818200 },
        { 0x3d403194, 0x80303 },
        { 0x3d4031b4, 0x100 },
-       { 0x3d4030f4, 0xc99 },
+       { 0x3d4030f4, 0x599 },
        { 0x3d400028, 0x0 },
 };
 
@@ -2076,7 +2078,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x110 },