fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd

diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c
index 60185d7aa4bf7e1b91fae01bec2a74796020f108..4a9f4eef8d291b9a9dae4a7b6b053e56d6d68756 100644 (file)
--- a/plat/imx/imx8m/ddr/dram.c
+++ b/plat/imx/imx8m/ddr/dram.c
@@ -30,6 +30,39 @@ static uint32_t fsp_init_reg[3][4] = {
        { DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) },
 };
 
+#if defined(PLAT_imx8mp)
+static uint32_t lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+       unsigned int tmp, drate_byte;
+
+       tmp = mmio_read_32(DRC_PERF_MON_MRR0_DAT(0));
+       mmio_write_32(DRC_PERF_MON_MRR0_DAT(0), tmp | 0x1);
+       do {
+               tmp = mmio_read_32(DDRC_MRSTAT(0));
+       } while (tmp & 0x1);
+
+       mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+       mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8));
+       mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4) | BIT(31) | 0x1);
+
+       /* Workaround for SNPS STAR 9001549457 */
+       do {
+               tmp = mmio_read_32(DDRC_MRSTAT(0));
+       } while (tmp & 0x1);
+
+       do {
+               tmp = mmio_read_32(DRC_PERF_MON_MRR0_DAT(0));
+       } while (!(tmp & 0x8));
+       tmp = mmio_read_32(DRC_PERF_MON_MRR1_DAT(0));
+
+       drate_byte = (mmio_read_32(DDRC_DERATEEN(0)) >> 4) & 0xff;
+       tmp = (tmp >> (drate_byte * 8)) & 0xff;
+       mmio_write_32(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+
+       return tmp;
+}
+#endif
+
 static void get_mr_values(uint32_t (*mr_value)[8])
 {
        uint32_t init_val;
@@ -41,6 +74,13 @@ static void get_mr_values(uint32_t (*mr_value)[8])
                        mr_value[fsp_index][2*i] = init_val >> 16;
                        mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF;
                }
+
+#if defined(PLAT_imx8mp)
+               if (dram_info.dram_type == DDRC_LPDDR4) {
+                       mr_value[fsp_index][5] = lpddr4_mr_read(1, MR12); /* read MR12 from DRAM */
+                       mr_value[fsp_index][7] = lpddr4_mr_read(1, MR14); /* read MR14 from DRAM */
+               }
+#endif
        }
 }
 

diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 14cb7099f80ff816fb5b64d068d70b82c5c52299..128127052e3122dabf51b42c0cacb7c028fedb32 100644 (file)
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2022 NXP
+ * Copyright 2020-2023 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -112,7 +112,7 @@
 #define IMX_DDRC_BASE                  U(0x3d400000)
 #define IMX_DDRPHY_BASE                        U(0x3c000000)
 #define IMX_DDR_IPS_BASE               U(0x3d000000)
-#define IMX_DDR_IPS_SIZE               U(0x1800000)
+#define IMX_DDR_IPS_SIZE               U(0x1900000)
 #define IMX_ROM_BASE                   U(0x0)
 #define IMX_ROM_SIZE                   U(0x40000)
 #define IMX_NS_OCRAM_BASE              U(0x900000)

diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h
index e8caa21f86b2d03ef7c869598479a2b5918c59bf..719c39063778fb21be05096cfa8183ca6d74d9e1 100644 (file)
--- a/plat/imx/imx8m/include/dram.h
+++ b/plat/imx/imx8m/include/dram.h
@@ -23,6 +23,9 @@
 #define DDRC_ACTIVE_ONE_RANK   U(0x1)
 #define DDRC_ACTIVE_TWO_RANK   U(0x2)
 
+#define MR12                   U(12)
+#define MR14                   U(14)
+
 #define MAX_FSP_NUM            U(3)
 
 /* reg & config param */