]> git.baikalelectronics.ru Git - kernel.git/commitdiff
qed: Add APIs for reading config id attributes.
authorSudarsana Reddy Kalluru <skalluru@marvell.com>
Fri, 30 Aug 2019 07:42:03 +0000 (00:42 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sat, 31 Aug 2019 20:32:30 +0000 (13:32 -0700)
The patch adds driver support for reading the config id attributes from NVM
flash partition.

Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed_main.c
drivers/net/ethernet/qlogic/qed/qed_mcp.c
drivers/net/ethernet/qlogic/qed/qed_mcp.h
include/linux/qed/qed_if.h

index 7891f8c5a1bcc3c9b9a5d38cd3c44749c595244f..c9a757177366a6a48eefd7333cd8795b8edd656b 100644 (file)
@@ -69,6 +69,8 @@
 #define QED_RDMA_SRQS                   QED_ROCE_QPS
 #define QED_NVM_CFG_SET_FLAGS          0xE
 #define QED_NVM_CFG_SET_PF_FLAGS       0x1E
+#define QED_NVM_CFG_GET_FLAGS          0xA
+#define QED_NVM_CFG_GET_PF_FLAGS       0x1A
 
 static char version[] =
        "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
@@ -2298,6 +2300,30 @@ static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
        return rc;
 }
 
+static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data,
+                                 u32 cmd, u32 entity_id)
+{
+       struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *ptt;
+       u32 flags, len;
+       int rc = 0;
+
+       ptt = qed_ptt_acquire(hwfn);
+       if (!ptt)
+               return -EAGAIN;
+
+       DP_VERBOSE(cdev, NETIF_MSG_DRV,
+                  "Read config cmd = %d entity id %d\n", cmd, entity_id);
+       flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS;
+       rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len);
+       if (rc)
+               DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
+
+       qed_ptt_release(hwfn, ptt);
+
+       return rc;
+}
+
 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
 {
        const struct firmware *image;
@@ -2610,6 +2636,7 @@ const struct qed_common_ops qed_common_ops_pass = {
        .db_recovery_del = &qed_db_recovery_del,
        .read_module_eeprom = &qed_read_module_eeprom,
        .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
+       .read_nvm_cfg = &qed_nvm_flash_cfg_read,
 };
 
 void qed_get_protocol_stats(struct qed_dev *cdev,
index 89462c4a50227540d6f0153b4e6d1688c57ecdae..36ddb89856a869cce7087c086888d71206f6e9bd 100644 (file)
@@ -3751,6 +3751,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
        return 0;
 }
 
+int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+                       u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
+                       u32 *p_len)
+{
+       u32 mb_param = 0, resp, param;
+       int rc;
+
+       QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
+       if (flags & QED_NVM_CFG_OPTION_INIT)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
+       if (flags & QED_NVM_CFG_OPTION_FREE)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
+       if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
+                                 entity_id);
+       }
+
+       rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
+                               DRV_MSG_CODE_GET_NVM_CFG_OPTION,
+                               mb_param, &resp, &param, p_len, (u32 *)p_buf);
+
+       return rc;
+}
+
 int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
                        u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
                        u32 len)
index 83649a82977b9e42615cfa3a85018e24dbf7dff9..9c4c2763de8d79998a65fe36ef97ada9ec1b8519 100644 (file)
@@ -1208,6 +1208,21 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
  */
 int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 
+/**
+ * @brief Get NVM config attribute value.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ * @param option_id
+ * @param entity_id
+ * @param flags
+ * @param p_buf
+ * @param p_len
+ */
+int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+                       u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
+                       u32 *p_len);
+
 /**
  * @brief Set NVM config attribute value.
  *
index e366399874f393ee1cd27df24c941831ce6eec96..06fd9580c9e50ea97860a2241c5a5853bf199a69 100644 (file)
@@ -1132,6 +1132,17 @@ struct qed_common_ops {
  * @param cdev
  */
        u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
+
+/**
+ * @brief read_nvm_cfg - Read NVM config attribute value.
+ * @param cdev
+ * @param buf - buffer
+ * @param cmd - NVM CFG command id
+ * @param entity_id - Entity id
+ *
+ */
+       int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
+                           u32 entity_id);
 };
 
 #define MASK_FIELD(_name, _value) \