]> git.baikalelectronics.ru Git - kernel.git/commitdiff
ath11k: Add qcn9074 mhi controller config
authorAnilkumar Kolli <akolli@codeaurora.org>
Tue, 16 Feb 2021 07:16:08 +0000 (09:16 +0200)
committerKalle Valo <kvalo@codeaurora.org>
Wed, 17 Feb 2021 09:32:40 +0000 (11:32 +0200)
Add MHI config for QCN9074 also populate ath11k_hw_params for QCN9074.

Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1

Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1612946530-28504-6-git-send-email-akolli@codeaurora.org
drivers/net/wireless/ath/ath11k/core.c
drivers/net/wireless/ath/ath11k/core.h
drivers/net/wireless/ath/ath11k/mhi.c
drivers/net/wireless/ath/ath11k/qmi.h

index 9ccc7231afa0147def906cd4a76a8b7281bfcd45..fa452de4945772bc976166da6a3fc30593e68ec1 100644 (file)
@@ -147,6 +147,18 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = false,
                .supports_suspend = true,
        },
+       {
+               .name = "qcn9074 hw1.0",
+               .hw_rev = ATH11K_HW_QCN9074_HW10,
+               .fw = {
+                       .dir = "QCN9074/hw1.0",
+                       .board_size = 256 * 1024,
+                       .cal_size = 256 * 1024,
+               },
+               .max_radios = 1,
+               .single_pdev_only = false,
+               .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
+       },
 };
 
 int ath11k_core_suspend(struct ath11k_base *ab)
index 8d29845774dfa7554bed46833837edda4431cf77..9a8fb23577b09621ee3d09c8027ff36147048c6b 100644 (file)
@@ -105,6 +105,7 @@ enum ath11k_hw_rev {
        ATH11K_HW_IPQ8074,
        ATH11K_HW_QCA6390_HW20,
        ATH11K_HW_IPQ6018_HW10,
+       ATH11K_HW_QCN9074_HW10,
 };
 
 enum ath11k_firmware_mode {
index 09858e516903ea7c694a6f770d1bb2387e987045..626764da4d6f9131a9541189f93d6fe252349b77 100644 (file)
@@ -7,10 +7,11 @@
 #include "core.h"
 #include "debug.h"
 #include "mhi.h"
+#include "pci.h"
 
 #define MHI_TIMEOUT_DEFAULT_MS 90000
 
-static struct mhi_channel_config ath11k_mhi_channels[] = {
+static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
        {
                .num = 0,
                .name = "LOOPBACK",
@@ -69,7 +70,7 @@ static struct mhi_channel_config ath11k_mhi_channels[] = {
        },
 };
 
-static struct mhi_event_config ath11k_mhi_events[] = {
+static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
        {
                .num_elements = 32,
                .irq_moderation_ms = 0,
@@ -92,15 +93,108 @@ static struct mhi_event_config ath11k_mhi_events[] = {
        },
 };
 
-static struct mhi_controller_config ath11k_mhi_config = {
+static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
        .max_channels = 128,
        .timeout_ms = 2000,
        .use_bounce_buf = false,
        .buf_len = 0,
-       .num_channels = ARRAY_SIZE(ath11k_mhi_channels),
-       .ch_cfg = ath11k_mhi_channels,
-       .num_events = ARRAY_SIZE(ath11k_mhi_events),
-       .event_cfg = ath11k_mhi_events,
+       .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
+       .ch_cfg = ath11k_mhi_channels_qca6390,
+       .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
+       .event_cfg = ath11k_mhi_events_qca6390,
+};
+
+static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
+       {
+               .num = 0,
+               .name = "LOOPBACK",
+               .num_elements = 32,
+               .event_ring = 1,
+               .dir = DMA_TO_DEVICE,
+               .ee_mask = 0x14,
+               .pollcfg = 0,
+               .doorbell = MHI_DB_BRST_DISABLE,
+               .lpm_notify = false,
+               .offload_channel = false,
+               .doorbell_mode_switch = false,
+               .auto_queue = false,
+       },
+       {
+               .num = 1,
+               .name = "LOOPBACK",
+               .num_elements = 32,
+               .event_ring = 1,
+               .dir = DMA_FROM_DEVICE,
+               .ee_mask = 0x14,
+               .pollcfg = 0,
+               .doorbell = MHI_DB_BRST_DISABLE,
+               .lpm_notify = false,
+               .offload_channel = false,
+               .doorbell_mode_switch = false,
+               .auto_queue = false,
+       },
+       {
+               .num = 20,
+               .name = "IPCR",
+               .num_elements = 32,
+               .event_ring = 1,
+               .dir = DMA_TO_DEVICE,
+               .ee_mask = 0x14,
+               .pollcfg = 0,
+               .doorbell = MHI_DB_BRST_DISABLE,
+               .lpm_notify = false,
+               .offload_channel = false,
+               .doorbell_mode_switch = false,
+               .auto_queue = false,
+       },
+       {
+               .num = 21,
+               .name = "IPCR",
+               .num_elements = 32,
+               .event_ring = 1,
+               .dir = DMA_FROM_DEVICE,
+               .ee_mask = 0x14,
+               .pollcfg = 0,
+               .doorbell = MHI_DB_BRST_DISABLE,
+               .lpm_notify = false,
+               .offload_channel = false,
+               .doorbell_mode_switch = false,
+               .auto_queue = true,
+       },
+};
+
+static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
+       {
+               .num_elements = 32,
+               .irq_moderation_ms = 0,
+               .irq = 1,
+               .data_type = MHI_ER_CTRL,
+               .mode = MHI_DB_BRST_DISABLE,
+               .hardware_event = false,
+               .client_managed = false,
+               .offload_channel = false,
+       },
+       {
+               .num_elements = 256,
+               .irq_moderation_ms = 1,
+               .irq = 2,
+               .mode = MHI_DB_BRST_DISABLE,
+               .priority = 1,
+               .hardware_event = false,
+               .client_managed = false,
+               .offload_channel = false,
+       },
+};
+
+static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
+       .max_channels = 30,
+       .timeout_ms = 10000,
+       .use_bounce_buf = false,
+       .buf_len = 0,
+       .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
+       .ch_cfg = ath11k_mhi_channels_qcn9074,
+       .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
+       .event_cfg = ath11k_mhi_events_qcn9074,
 };
 
 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
@@ -221,6 +315,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 {
        struct ath11k_base *ab = ab_pci->ab;
        struct mhi_controller *mhi_ctrl;
+       struct mhi_controller_config *ath11k_mhi_config;
        int ret;
 
        mhi_ctrl = mhi_alloc_controller();
@@ -254,7 +349,12 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
        mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
        mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
 
-       ret = mhi_register_controller(mhi_ctrl, &ath11k_mhi_config);
+       if (ab->hw_rev == ATH11K_HW_QCA6390_HW20)
+               ath11k_mhi_config = &ath11k_mhi_config_qca6390;
+       else if (ab->hw_rev == ATH11K_HW_QCN9074_HW10)
+               ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
+
+       ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
        if (ret) {
                ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
                mhi_free_controller(mhi_ctrl);
index a7d01c295e7718563bb51d7419e339efc6195fa2..3d593033070321cda3a094cb3a1ef3f95abcc478 100644 (file)
@@ -21,6 +21,7 @@
 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01     0x02
 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390     0x01
 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074     0x02
+#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074     0x07
 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01        32
 #define ATH11K_QMI_RESP_LEN_MAX                        8192
 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01  52