]> git.baikalelectronics.ru Git - uboot.git/commitdiff
arm: socfpga: soc64: Add ATF support for Reset Manager driver
authorChee Hong Ang <chee.hong.ang@intel.com>
Thu, 24 Dec 2020 10:21:06 +0000 (18:21 +0800)
committerLey Foon Tan <ley.foon.tan@intel.com>
Fri, 15 Jan 2021 09:48:37 +0000 (17:48 +0800)
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
arch/arm/mach-socfpga/reset_manager_s10.c

index 3746e6a60c3c1188c177b758c8df958cee70fdf0..af8f2c0873104b96eb9c70f8949b7fbe74e3c997 100644 (file)
@@ -5,11 +5,14 @@
  */
 
 #include <common.h>
+#include <hang.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 #include <linux/iopoll.h>
+#include <linux/intel-smc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
 
 void socfpga_bridges_reset(int enable)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+       u64 arg = enable;
+
+       int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+       if (ret) {
+               printf("SMC call failed with error %d in %s.\n", ret, __func__);
+               return;
+       }
+#else
        u32 reg;
 
        if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
                /* Disable NOC timeout */
                writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
        }
+#endif
 }
 
 /*