]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/amdgpu: set TMZ bits in PTEs for secure BO (v4)
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 8 Aug 2019 03:32:46 +0000 (22:32 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 28 Apr 2020 20:20:29 +0000 (16:20 -0400)
If a buffer object is secure, i.e. created with
AMDGPU_GEM_CREATE_ENCRYPTED, then the TMZ bit of
the PTEs that belong the buffer object should be
set.

v1: design and draft the skeletion of TMZ bits setting on PTEs (Alex)
v2: return failure once create secure BO on non-TMZ platform  (Ray)
v3: amdgpu_bo_encrypted() only checks the BO (Luben)
v4: move TMZ flag setting into amdgpu_vm_bo_update  (Christian)

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 32f36c940abb5a9eb922c79cf9af97192ec85c1a..26220ee87291f43d37308befe0a9dd18edd9e6da 100644 (file)
@@ -233,7 +233,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
                      AMDGPU_GEM_CREATE_VRAM_CLEARED |
                      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
-                     AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+                     AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
+                     AMDGPU_GEM_CREATE_ENCRYPTED))
 
                return -EINVAL;
 
@@ -241,6 +242,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
        if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
                return -EINVAL;
 
+       if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
+               DRM_ERROR("Cannot allocate secure buffer while tmz is disabled\n");
+               return -EINVAL;
+       }
+
        /* create a gem object to contain this object in */
        if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
            AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -262,6 +268,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                resv = vm->root.base.bo->tbo.base.resv;
        }
 
+       if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
+               /* XXX: pad out alignment to meet TMZ requirements */
+       }
+
        r = amdgpu_gem_object_create(adev, size, args->in.alignment,
                                     (u32)(0xffffffff & args->in.domains),
                                     flags, ttm_bo_type_device, resv, &gobj);
index 5e39ecd8cc28d099f31ba23e3dcbfa8d9fae515d..7d41f7b9a340574c3422e1ef9a570a27b51351cd 100644 (file)
@@ -229,6 +229,17 @@ static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
        return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
 }
 
+/**
+ * amdgpu_bo_encrypted - test if the BO is encrypted
+ * @bo: pointer to a buffer object
+ *
+ * Return true if the buffer object is encrypted, false otherwise.
+ */
+static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
+{
+       return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
+}
+
 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 
index bcdaf5204d05e76a11711a8c274ac9b652a23707..0d82105530597474a357bc3883bbd01b5ed59612 100644 (file)
@@ -1784,6 +1784,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 
        if (bo) {
                flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
+
+               if (amdgpu_bo_encrypted(bo))
+                       flags |= AMDGPU_PTE_TMZ;
+
                bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
        } else {
                flags = 0x0;