]> git.baikalelectronics.ru Git - uboot.git/commitdiff
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
authorAng, Chee Hong <chee.hong.ang@intel.com>
Thu, 20 Dec 2018 02:35:15 +0000 (18:35 -0800)
committerMarek Vasut <marex@denx.de>
Thu, 20 Dec 2018 16:12:25 +0000 (17:12 +0100)
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
arch/arm/mach-socfpga/include/mach/misc.h
arch/arm/mach-socfpga/misc.c
arch/arm/mach-socfpga/misc_arria10.c
arch/arm/mach-socfpga/misc_gen5.c
arch/arm/mach-socfpga/misc_s10.c
drivers/fpga/altera.c
include/altera.h

index 26609927c834ae2f035bb8a93bd4c5241ba8018d..86d5d2b62b079aed4afafbb91d9d3c81f3154d4c 100644 (file)
@@ -18,9 +18,9 @@ struct bsel {
 extern struct bsel bsel_str[];
 
 #ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
+void socfpga_fpga_add(void *fpga_desc);
 #else
-static inline void socfpga_fpga_add(void) {}
+inline void socfpga_fpga_add(void *fpga_desc) {}
 #endif
 
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
index a4f6d5c1ac9967cfb384356d375571223d364c48..78fbe287244bae6bbdc44fc03c0e906a6208af9f 100644 (file)
@@ -88,33 +88,11 @@ int overwrite_console(void)
 #endif
 
 #ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
-       {
-               /* Family */
-               Altera_SoCFPGA,
-               /* Interface type */
-               fast_passive_parallel,
-               /* No limitation as additional data will be ignored */
-               -1,
-               /* No device function table */
-               NULL,
-               /* Base interface address specified in driver */
-               NULL,
-               /* No cookie implementation */
-               0
-       },
-};
-
 /* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
+void socfpga_fpga_add(void *fpga_desc)
 {
-       int i;
        fpga_init();
-       for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
-               fpga_add(fpga_altera, &altera_fpga[i]);
+       fpga_add(fpga_altera, fpga_desc);
 }
 #endif
 
index f347ae857e036bee4475f39509a6e9e4cb7861f5..63b8c75d31d134053ac521c62bded724315d8485 100644 (file)
 
 static struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Altera_SoCFPGA,
+               /* Interface type */
+               fast_passive_parallel,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
+};
+
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
        (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void)
 int arch_early_init_r(void)
 {
        /* Add device descriptor to FPGA device table */
-       socfpga_fpga_add();
+       socfpga_fpga_add(&altera_fpga[0]);
 
        return 0;
 }
index 5fa40937c405da8c0e07ff1b5a9739347a9d84af..04f237d100c61ef1b784f22d8edff8ef38566eb4 100644 (file)
@@ -34,6 +34,26 @@ static struct nic301_registers *nic301_regs =
 static struct scu_registers *scu_regs =
        (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Altera_SoCFPGA,
+               /* Interface type */
+               fast_passive_parallel,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
+};
+
 /*
  * DesignWare Ethernet initialization
  */
@@ -221,7 +241,7 @@ int arch_early_init_r(void)
        socfpga_sdram_remap_zero();
 
        /* Add device descriptor to FPGA device table */
-       socfpga_fpga_add();
+       socfpga_fpga_add(&altera_fpga[0]);
 
 #ifdef CONFIG_DESIGNWARE_SPI
        /* Get Designware SPI controller out of reset */
index e599362f145861abd6f57412c4c8d5784c59d92d..113eace650edcfe12f3afd2566868362d11ab8ea 100644 (file)
@@ -24,6 +24,26 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Intel_FPGA_Stratix10,
+               /* Interface type */
+               secure_device_manager_mailbox,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
+};
+
 /*
  * DesignWare Ethernet initialization
  */
@@ -125,6 +145,8 @@ int arch_misc_init(void)
 
 int arch_early_init_r(void)
 {
+       socfpga_fpga_add(&altera_fpga[0]);
+
        return 0;
 }
 
index 9605554c6aa571a11bc65f1f9f42fd712024cfe6..7c8f5185095a16d64bd491d76aa0bf639134e5cd 100644 (file)
@@ -39,6 +39,9 @@ static const struct altera_fpga {
 #if defined(CONFIG_FPGA_STRATIX_V)
        { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
 #endif
+#if defined(CONFIG_FPGA_STRATIX10)
+       { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
+#endif
 #if defined(CONFIG_FPGA_SOCFPGA)
        { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
 #endif
@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
        case fast_passive_parallel_security:
                printf("Fast Passive Parallel with Security (FPPS)\n");
                break;
+       case secure_device_manager_mailbox:
+               puts("Secure Device Manager (SDM) Mailbox\n");
+               break;
                /* Add new interface types here */
        default:
                printf("Unsupported interface type, %d\n", desc->iface);
index 233b467dba07b93d5c8a9fd7cabc05b3e1f7adcf..22d55cfd73e70dd17a979d1dc8d508053bd4f29e 100644 (file)
@@ -39,6 +39,8 @@ enum altera_iface {
        fast_passive_parallel,
        /* fast passive parallel with security (FPPS) */
        fast_passive_parallel_security,
+       /* secure device manager (SDM) mailbox */
+       secure_device_manager_mailbox,
        /* insert all new types before this */
        max_altera_iface_type,
 };
@@ -54,6 +56,8 @@ enum altera_family {
        Altera_StratixII,
        /* StratixV Family */
        Altera_StratixV,
+       /* Stratix10 Family */
+       Intel_FPGA_Stratix10,
        /* SoCFPGA Family */
        Altera_SoCFPGA,