fix(cpus): do not put RAS check before using esb

If RAS Extension is not implemented esb instruction executes as a NOP.
No need to have a check for RAS presence in the code.
Also, The handler is related to a synchronous exceptions which
implicitly is part of BL31 image only, so remove that check too.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If4264504cba9f0642b7b9c581ae66cd4deace32b

diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 827c0b0c7143a0cd2f5533a0dff30cdd1148d80e..2cf94c758e415f8a6ecf84f38b57879fb3f54991 100644 (file)
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -706,7 +706,6 @@ func neoverse_n1_errata_ic_trap_handler
        ldp     x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
        ldr     x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
 
-#if IMAGE_BL31 && RAS_EXTENSION
        /*
         * Issue Error Synchronization Barrier to synchronize SErrors before
         * exiting EL3. We're running with EAs unmasked, so any synchronized
@@ -714,7 +713,6 @@ func neoverse_n1_errata_ic_trap_handler
         * DISR_EL1 register.
         */
        esb
-#endif
        exception_return
 1:
        ret