u8 learn[DSA_MAX_PORTS];
int first, index, cnt;
struct ksz_port *p;
+ const u16 *regs;
+
+ regs = dev->info->regs;
if ((uint)port < dev->info->port_cnt) {
first = port;
p = &dev->ports[index];
if (!p->on)
continue;
- ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
+ ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
if (!(learn[index] & PORT_LEARN_DISABLE))
- ksz_pwrite8(dev, index, P_STP_CTRL,
+ ksz_pwrite8(dev, index, regs[P_STP_CTRL],
learn[index] | PORT_LEARN_DISABLE);
}
ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
if (!p->on)
continue;
if (!(learn[index] & PORT_LEARN_DISABLE))
- ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
+ ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
}
}
p->fiber = 1;
}
if (p->fiber)
- ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
- true);
+ ksz_port_cfg(dev, i, regs[P_STP_CTRL],
+ PORT_FORCE_FLOW_CTRL, true);
else
- ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
- false);
+ ksz_port_cfg(dev, i, regs[P_STP_CTRL],
+ PORT_FORCE_FLOW_CTRL, false);
}
}
void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
{
+ const u16 *regs = dev->info->regs;
u8 data;
regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
if (port < dev->info->port_cnt) {
/* flush individual port */
- ksz_pread8(dev, port, P_STP_CTRL, &data);
+ ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
if (!(data & PORT_LEARN_DISABLE))
- ksz_pwrite8(dev, port, P_STP_CTRL,
+ ksz_pwrite8(dev, port, regs[P_STP_CTRL],
data | PORT_LEARN_DISABLE);
ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
- ksz_pwrite8(dev, port, P_STP_CTRL, data);
+ ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
} else {
/* flush all */
ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
[P_REMOTE_STATUS] = 0x08,
[P_SPEED_STATUS] = 0x09,
[S_TAIL_TAG_CTRL] = 0x0C,
+ [P_STP_CTRL] = 0x02,
};
static const u32 ksz8795_masks[] = {
[P_REMOTE_STATUS] = 0x0E,
[P_SPEED_STATUS] = 0x0F,
[S_TAIL_TAG_CTRL] = 0x03,
+ [P_STP_CTRL] = 0x02,
};
static const u32 ksz8863_masks[] = {
[DYNAMIC_MAC_SRC_PORT] = 20,
};
+static const u16 ksz9477_regs[] = {
+ [P_STP_CTRL] = 0x0B04,
+
+};
+
const struct ksz_chip_data ksz_switch_chips[] = {
[KSZ8795] = {
.chip_id = KSZ8795_CHIP_ID,
.regs = ksz8795_regs,
.masks = ksz8795_masks,
.shifts = ksz8795_shifts,
- .stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
.multicast_ctrl_reg = 0x04,
.start_ctrl_reg = 0x01,
.regs = ksz8795_regs,
.masks = ksz8795_masks,
.shifts = ksz8795_shifts,
- .stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
.multicast_ctrl_reg = 0x04,
.start_ctrl_reg = 0x01,
.regs = ksz8795_regs,
.masks = ksz8795_masks,
.shifts = ksz8795_shifts,
- .stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
.multicast_ctrl_reg = 0x04,
.start_ctrl_reg = 0x01,
.regs = ksz8863_regs,
.masks = ksz8863_masks,
.shifts = ksz8863_shifts,
- .stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
.multicast_ctrl_reg = 0x04,
.start_ctrl_reg = 0x01,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
- .stp_ctrl_reg = 0x0B04,
+ .regs = ksz9477_regs,
.broadcast_ctrl_reg = 0x0332,
.multicast_ctrl_reg = 0x0331,
.start_ctrl_reg = 0x0300,
{
struct ksz_device *dev = ds->priv;
struct ksz_port *p;
+ const u16 *regs;
u8 data;
- int reg;
- reg = dev->info->stp_ctrl_reg;
+ regs = dev->info->regs;
- ksz_pread8(dev, port, reg, &data);
+ ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
switch (state) {
return;
}
- ksz_pwrite8(dev, port, reg, data);
+ ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
p = &dev->ports[port];
p->stp_state = state;