style: remove useless trailing semicolon and line continuations

found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c

diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index b70bffd914ae1f77fd6747dc64a73d797ab7ce11..6d4dc7e70f4a57044caacf9708d85ba28d2a69e0 100644 (file)
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c
@@ -420,7 +420,7 @@ static int bl1_fwu_image_auth(unsigned int image_id,
                 * Image is in RESET state.
                 * Check the parameters and authenticate the source image in place.
                 */
-               if (bl1_plat_mem_check(image_src, image_size,   \
+               if (bl1_plat_mem_check(image_src, image_size,
                                        desc->ep_info.h.attr) != 0) {
                        WARN("BL1-FWU: Authentication arguments source/size not mapped\n");
                        return -ENOMEM;

diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c
index 65fa85a9fc853253d105dce22fab522b915152d1..fb5b03679d10d593dab0ac8506d4a2acd5da7aee 100644 (file)
--- a/drivers/auth/mbedtls/mbedtls_x509_parser.c
+++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c
@@ -474,5 +474,5 @@ static int get_auth_param(const auth_param_type_desc_t *type_desc,
        return rc;
 }
 
-REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init, \
+REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init,
                       check_integrity, get_auth_param);

diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h
index 2ce7874ef27d83d8972c65d6b84683b62e239c13..8876da9e4720d76d3d4bd9d044885320b0d75b9d 100644 (file)
--- a/include/arch/aarch32/smccc_helpers.h
+++ b/include/arch/aarch32/smccc_helpers.h
@@ -90,21 +90,21 @@ typedef struct smc_ctx {
  * ensure that the assembler and the compiler view of the offsets of
  * the structure members is the same.
  */
-CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
+CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0),
        assert_smc_ctx_greg_r0_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
+CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1),
        assert_smc_ctx_greg_r1_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
+CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2),
        assert_smc_ctx_greg_r2_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
+CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3),
        assert_smc_ctx_greg_r3_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
+CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4),
        assert_smc_ctx_greg_r4_offset_mismatch);
-CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
+CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr),
        assert_smc_ctx_sp_usr_offset_mismatch);
-CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
+CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon),
        assert_smc_ctx_lr_mon_offset_mismatch);
-CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
+CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon),
        assert_smc_ctx_spsr_mon_offset_mismatch);
 
 CASSERT((sizeof(smc_ctx_t) & 0x7U) == 0U, assert_smc_ctx_not_aligned);

diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 5d99778c74d53b6b5ec6b77e83914835319c2921..3350c8f907baaf5763eec10c1f1a1eb8f0e9664f 100644 (file)
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -692,7 +692,7 @@ void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
        isb();  \
 }
 #else
-#define AT(_at_inst, _va)      _at_inst(_va);
+#define AT(_at_inst, _va)      _at_inst(_va)
 #endif
 
 #endif /* ARCH_HELPERS_H */

diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h
index 21d3ae7b7c0944ef94130339d425afe712a145cf..7cd7e727ca8fa43963871e71208ad781dfb16910 100644 (file)
--- a/include/bl1/bl1.h
+++ b/include/bl1/bl1.h
@@ -90,8 +90,8 @@ void bl1_plat_prepare_exit(entry_point_info_t *ep_info);
 /*
  * Check if the total number of FWU SMC calls are as expected.
  */
-CASSERT(FWU_NUM_SMC_CALLS ==   \
-               (FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\
+CASSERT(FWU_NUM_SMC_CALLS ==
+               (FWU_SMC_FID_END - FWU_SMC_FID_START + 1),
                assert_FWU_NUM_SMC_CALLS_mismatch);
 
 /* Utility functions */

diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h
index 4793e2f3c0ef641f68f641f8824c85c39df238f8..26e8d6f283bc5d23c1108714b1ed314772c9928f 100644 (file)
--- a/include/common/runtime_svc.h
+++ b/include/common/runtime_svc.h
@@ -90,11 +90,11 @@ typedef struct rt_svc_desc {
  * 3. ensure that the assembler and the compiler see the handler
  *    routine at the same offset.
  */
-CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \
+CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC),
        assert_sizeof_rt_svc_desc_mismatch);
-CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \
+CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init),
        assert_rt_svc_desc_init_offset_mismatch);
-CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \
+CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle),
        assert_rt_svc_desc_handle_offset_mismatch);
 
 

diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index 5604c8e502947b1fa68299bbaa2abca0d8382e72..df77c0ffb4cc3515f62511886de93345f61f8f59 100644 (file)
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -62,7 +62,7 @@ typedef struct cpu_context {
  * ensure that the assembler and the compiler view of the offsets of
  * the structure members is the same.
  */
-CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \
+CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx),
        assert_core_context_regs_offset_mismatch);
 
 #endif /* __ASSEMBLER__ */

diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 57cf5f04d9c0dbab1f65031e6a7e260ef7feb002..40bfa39c6bf0d7fc3055e9a1950a1c1f039a1a55 100644 (file)
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -445,24 +445,24 @@ typedef struct cpu_context {
  * ensure that the assembler and the compiler view of the offsets of
  * the structure members is the same.
  */
-CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
+CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx),
        assert_core_context_gp_offset_mismatch);
-CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \
+CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx),
        assert_core_context_el1_sys_offset_mismatch);
 #if CTX_INCLUDE_EL2_REGS
-CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \
+CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx),
        assert_core_context_el2_sys_offset_mismatch);
 #endif
 #if CTX_INCLUDE_FPREGS
-CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
+CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx),
        assert_core_context_fp_offset_mismatch);
 #endif
-CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
+CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
        assert_core_context_el3state_offset_mismatch);
-CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \
+CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx),
        assert_core_context_cve_2018_3639_offset_mismatch);
 #if CTX_INCLUDE_PAUTH_REGS
-CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \
+CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
        assert_core_context_pauth_offset_mismatch);
 #endif
 

diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index faea6c53d0d5dc6f01c294e4b666d55309c9a235..3c03ae604df9525a9fe8fd3ccb41533b9a9d7308 100644 (file)
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -44,7 +44,7 @@
  * Using this value, if provided, rather than the linker generated value results in
  * more efficient code
  */
-CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
+CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0,
        PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple);
 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE)
 #else

diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index 1e207a4dd27dcdc4e2e280d555d4d83eb25f8efd..5646f347cf7ced3c5025cbfe0bf60e7940f68358 100644 (file)
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -518,9 +518,9 @@ void enable_mmu_svc_mon(unsigned int flags)
        /* Enable Access flag (simplified access permissions) and TEX remap */
        write_sctlr(read_sctlr() | SCTLR_AFE_BIT | SCTLR_TRE_BIT);
 
-       prrr = MMU32B_PRRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 1, 0) \
+       prrr = MMU32B_PRRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 1, 0)
                        | MMU32B_PRRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 2, 1);
-       nmrr = MMU32B_NMRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 0, 0) \
+       nmrr = MMU32B_NMRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 0, 0)
                        | MMU32B_NMRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 1, 1);
 
        prrr |= MMU32B_PRRR_NS1 | MMU32B_PRRR_DS1;

diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index c7bf93e602f7f214095d39731204c9aa4e74b6d3..016de2ad1fb7eb1309ea3d2d490fea91155362a5 100644 (file)
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -180,8 +180,8 @@ const mmap_region_t plat_arm_mmap[] = {
 #if defined(IMAGE_BL31) && SPM_MM
 const mmap_region_t plat_arm_secure_partition_mmap[] = {
        V2M_MAP_IOFPGA_EL0, /* for the UART */
-       MAP_REGION_FLAT(DEVICE0_BASE,                           \
-                       DEVICE0_SIZE,                           \
+       MAP_REGION_FLAT(DEVICE0_BASE,
+                       DEVICE0_SIZE,
                        MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
        ARM_SP_IMAGE_MMAP,
        ARM_SP_IMAGE_NS_BUF_MMAP,

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
index 1ac0a9c3c231a1f1c7815514c06e2b06918f2189..a6429295984273ee9e6dde3ef6a8d424750572a1 100644 (file)
--- a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
@@ -109,10 +109,10 @@ void arm_bl1_plat_arch_setup(void)
                ARM_MAP_BL_COHERENT_RAM,
 #endif
                /* DRAM1_region: */
-               MAP_REGION_FLAT(                                        \
-                       PLAT_ARM_DRAM1_BASE,                            \
-                       PLAT_ARM_DRAM1_SIZE,                            \
-                       MT_MEMORY | MT_SECURE | MT_EXECUTE              \
+               MAP_REGION_FLAT(
+                       PLAT_ARM_DRAM1_BASE,
+                       PLAT_ARM_DRAM1_SIZE,
+                       MT_MEMORY | MT_SECURE | MT_EXECUTE
                        | MT_RW | MT_NON_CACHEABLE),
                /* NULL terminator: */
                {0}

diff --git a/plat/arm/board/rde1edge/rde1edge_topology.c b/plat/arm/board/rde1edge/rde1edge_topology.c
index a16283e450bbafd88321ebaf4bc0ddc0921961ea..91cc37e1cc4816d7d9df59a6d8e7a8fb8d80265c 100644 (file)
--- a/plat/arm/board/rde1edge/rde1edge_topology.c
+++ b/plat/arm/board/rde1edge/rde1edge_topology.c
@@ -31,6 +31,6 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
  * to the SCMI power domain ID implemented by SCP.
  ******************************************************************************/
 const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-       0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,           \
+       0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
        16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
 };

diff --git a/plat/arm/common/aarch64/arm_sdei.c b/plat/arm/common/aarch64/arm_sdei.c
index 3c74a465c690072c4924b5a0ec27790b7ef5cdbc..2e76118d0f5274ba79da652e2e291c3cd34a557a 100644 (file)
--- a/plat/arm/common/aarch64/arm_sdei.c
+++ b/plat/arm/common/aarch64/arm_sdei.c
@@ -38,7 +38,7 @@ void plat_sdei_setup(void)
        }
 
        for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_cnt); i++) {
-               arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT( \
+               arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT(
                        FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_nums[i]),
                        FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_intrs[i]),
                        FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_flags[i]));

diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index 5434c94571eee81a59c133bcc808cfe8d030936c..62cc8bbcfb5883e43e976ede1a5666ab78a59724 100644 (file)
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -191,7 +191,7 @@ void plat_arm_program_trusted_mailbox(uintptr_t address)
         * ARM_SHARED_RAM region.
         */
        assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
-               ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
+               ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <=
                                (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
 }
 

diff --git a/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
index 8f5555459ddfe21cdfa873da8680f0281c4536de..4c9f4afc4ab3a1a732626f65d9e3c23c967bb514 100644 (file)
--- a/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
+++ b/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
@@ -84,7 +84,7 @@ static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
 void tegra_fc_ccplex_pgexit_lock(void)
 {
        unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
-       uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;;
+       uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;
        uint32_t icept_cpu_flags[] = {
                INTERCEPT_EXIT_PG_CORE0,
                INTERCEPT_EXIT_PG_CORE1,

diff --git a/plat/nvidia/tegra/drivers/pmc/pmc.c b/plat/nvidia/tegra/drivers/pmc/pmc.c
index 6c5a73bafd86a35df1b8cd31e4ae6b3fbb8a07bf..e70e7a6c1d7c9145ccf852a80f5e84eac821a120 100644 (file)
--- a/plat/nvidia/tegra/drivers/pmc/pmc.c
+++ b/plat/nvidia/tegra/drivers/pmc/pmc.c
@@ -103,7 +103,7 @@ void tegra_pmc_lock_cpu_vectors(void)
 bool tegra_pmc_is_last_on_cpu(void)
 {
        int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
-       uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);;
+       uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
        bool status = true;
 
        /* check if this is the last standing CPU */

diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index a57bc11b9c86f1db287970b36f11d5258798af8a..6414e07e64ff05f45fb5eefbef16dc399a422537 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -372,8 +372,8 @@ int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
         * StandbyWFI or the equivalent signal, and always keeping the IDLE
         * voltage/frequency request register enabled.
         */
-       val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
-               ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
+       val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |
+               ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |
                ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
 
        return ari_request_wait(ari_base, 0U,

diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index cbc9aa3a6897780f9009bd61dadd745540f60265..1a48563240af67f73ce7df75f66fddec617bc89f 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -246,8 +246,8 @@ int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
         * StandbyWFI or the equivalent signal, and always keeping the IDLE
         * voltage/frequency request register enabled.
         */
-       val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
-               ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
+       val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |
+               ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |
                ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
 
        nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);

diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 310e95104a59e5d1e5bd4fb5837137338dddb19a..710d5c53ea1b5cc74b2d981a0fd27715778a3759 100644 (file)
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -24,7 +24,7 @@ static uint32_t tegra_misc_read_32(uint32_t off)
 uint32_t plat_get_num_smmu_devices(void)
 {
        uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
-       uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
+       uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >>
                                                        BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
 
        if (board_revid == BOARD_SYSTEM_FPGA_BASE) {

diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.h b/plat/rockchip/rk3399/drivers/dp/cdn_dp.h
index c5cbae2ef22622fb3532267e43e3eadd93edee82..52c72d638920669ef22d1f2553ad61663a95aed3 100644 (file)
--- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.h
+++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.h
@@ -34,7 +34,7 @@ struct cdn_dp_hdcp_key_1x {
 #define HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE      (6 * 64) / 8
 
 /* Checks the cdn_dp_hdcp_key_1x must be aligned on 6 x 64-bit word boundary */
-CASSERT(sizeof(struct cdn_dp_hdcp_key_1x) % HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE, \
+CASSERT(sizeof(struct cdn_dp_hdcp_key_1x) % HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE,
        assert_hdcp_key_1x_store_data_align_size_mismatch);
 
 uint64_t dp_hdcp_ctrl(uint64_t type);

diff --git a/services/spd/opteed/opteed_private.h b/services/spd/opteed/opteed_private.h
index ab6e4cd0aecf02580cde95a242637038d47c5615..c8fbc221f946fe17f6ee8266e63711e6444aa50c 100644 (file)
--- a/services/spd/opteed/opteed_private.h
+++ b/services/spd/opteed/opteed_private.h
@@ -114,7 +114,7 @@ DEFINE_REG_STRUCT(c_rt_regs, OPTEED_C_RT_CTX_ENTRIES);
  * have the same double word aligned view of the size of the C runtime
  * register context.
  */
-CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),   \
+CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
        assert_spd_c_rt_regs_size_mismatch);
 
 /*******************************************************************************

diff --git a/services/spd/tlkd/tlkd_private.h b/services/spd/tlkd/tlkd_private.h
index 5d5d0e8590cb19ef1a84e028f86bada02e48f678..ad36f5e4b82064f99d3ee9c5f6cdb4b6e7869c46 100644 (file)
--- a/services/spd/tlkd/tlkd_private.h
+++ b/services/spd/tlkd/tlkd_private.h
@@ -85,7 +85,7 @@ DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES);
  * have the same double word aligned view of the size of the C runtime
  * register context.
  */
-CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),     \
+CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
        assert_tlkd_c_rt_regs_size_mismatch);
 
 /*******************************************************************************

diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h
index d6c03c97319aca09138ebe533e3d9a1f3c202a9a..043644a15e4260fd1df8ed43c92a696096255e43 100644 (file)
--- a/services/spd/tspd/tspd_private.h
+++ b/services/spd/tspd/tspd_private.h
@@ -146,7 +146,7 @@ DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
  * have the same double word aligned view of the size of the C runtime
  * register context.
  */
-CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),     \
+CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
        assert_spd_c_rt_regs_size_mismatch);
 
 /* SEL1 Secure payload (SP) caller saved register context structure. */
@@ -157,7 +157,7 @@ DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES);
  * have the same double word aligned view of the size of the C runtime
  * register context.
  */
-CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t),     \
+CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t),
        assert_spd_sp_regs_size_mismatch);
 
 /*******************************************************************************