MIPS: Add & use CP0_EntryHi ASID definitions

Add definitions for the ASID field in CP0_EntryHi (along with the soon
to be used ASIDX field), and use them in a few previously hardcoded
cases.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13205/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1e9d337fb077aea2ebefdcc176582b1ccd8c69e9..b7705ef09df23c228e7ead8d62189fadeb70492e 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -229,6 +229,8 @@
 
 /* MIPS32/64 EntryHI bit definitions */
 #define MIPS_ENTRYHI_EHINV     (_ULCAST_(1) << 10)
+#define MIPS_ENTRYHI_ASIDX     (_ULCAST_(0x3) << 8)
+#define MIPS_ENTRYHI_ASID      (_ULCAST_(0xff) << 0)
 
 /*
  * R4x00 interrupt enable / cause bits

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index baa7b6fc0a60b1879976c2d4158f73d01e0ca53b..17374aef6f00f83edac2aec3b8adca63a8cbe49a 100644 (file)
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -455,7 +455,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
        .set    noreorder
        /* check if TLB contains a entry for EPC */
        MFC0    k1, CP0_ENTRYHI
-       andi    k1, 0xff        /* ASID_MASK */
+       andi    k1, MIPS_ENTRYHI_ASID
        MFC0    k0, CP0_EPC
        PTR_SRL k0, _PAGE_SHIFT + 1
        PTR_SLL k0, _PAGE_SHIFT + 1

diff --git a/arch/mips/kvm/locore.S b/arch/mips/kvm/locore.S
index c24facc8535717755dc7949cb026cb8219b8db97..308706493fd5f0950df9b11d5a62c6610a0809d1 100644 (file)
--- a/arch/mips/kvm/locore.S
+++ b/arch/mips/kvm/locore.S
@@ -164,7 +164,7 @@ FEXPORT(__kvm_mips_load_asid)
        INT_SLL t2, t2, 2                   /* x4 */
        REG_ADDU t3, t1, t2
        LONG_L  k0, (t3)
-       andi    k0, k0, 0xff
+       andi    k0, k0, MIPS_ENTRYHI_ASID
        mtc0    k0, CP0_ENTRYHI
        ehb
 
@@ -483,7 +483,7 @@ __kvm_mips_return_to_guest:
        INT_SLL t2, t2, 2               /* x4 */
        REG_ADDU t3, t1, t2
        LONG_L  k0, (t3)
-       andi    k0, k0, 0xff
+       andi    k0, k0, MIPS_ENTRYHI_ASID
        mtc0    k0, CP0_ENTRYHI
        ehb
 

diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 28952637a862b3a94fd45040f4a692c322c1730b..c8994c156e2ddad2c0bde912c553f66015c8d757 100644 (file)
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -76,7 +76,7 @@ static void mod_wired_entry(int entry, unsigned long entrylo0,
        unsigned long old_ctx;
 
        /* Save old context and create impossible VPN2 value */
-       old_ctx = read_c0_entryhi() & 0xff;
+       old_ctx = read_c0_entryhi() & MIPS_ENTRYHI_ASID;
        old_pagemask = read_c0_pagemask();
        write_c0_index(entry);
        write_c0_pagemask(pagemask);