MIPS: Loongson-3: Set cache flush handlers to cache_noop

Loongson-3 maintains cache coherency by hardware, this means:
 1) It's icache is coherent with dcache.
 2) It's dcaches don't alias (maybe depend on PAGE_SIZE).
 3) It maintains cache coherency across cores (and for DMA).

So we can skip most cache flush operations by setting relevant handlers
to `cache_noop' in `r4k_cache_init'.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12752/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 77fbaf1cdfd635d6848b81e0f31d507ef4554342..3415d3e2a63bddcba9c87ffdb43bfaad817e4183 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1796,6 +1796,20 @@ void r4k_cache_init(void)
                /* Optimization: an L2 flush implicitly flushes the L1 */
                current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
                break;
+       case CPU_LOONGSON3:
+               /* Loongson-3 maintains cache coherency by hardware */
+               __flush_cache_all       = cache_noop;
+               __flush_cache_vmap      = cache_noop;
+               __flush_cache_vunmap    = cache_noop;
+               __flush_kernel_vmap_range = (void *)cache_noop;
+               flush_cache_mm          = (void *)cache_noop;
+               flush_cache_page        = (void *)cache_noop;
+               flush_cache_range       = (void *)cache_noop;
+               flush_cache_sigtramp    = (void *)cache_noop;
+               flush_icache_all        = (void *)cache_noop;
+               flush_data_cache_page   = (void *)cache_noop;
+               local_flush_data_cache_page     = (void *)cache_noop;
+               break;
        }
 }