Support USB2/3 functionality in simple SoC integrations with
USB controller based on the DesignWare USB3 IP Core.
+config USB_XHCI_EXYNOS
+ bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
+ depends on ARCH_EXYNOS5
+ default y
+ help
+ Enables support for he on-chip xHCI controller on Samsung Exynos5
+ SoCs.
+
config USB_XHCI_MTK
bool "Support for MediaTek on-chip xHCI USB controller"
depends on ARCH_MEDIATEK
---help---
Enables support for the on-chip EHCI controller on Atmel chips.
+config USB_EHCI_EXYNOS
+ bool "Support for Samsung Exynos EHCI USB controller"
+ depends on ARCH_EXYNOS
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on Samsung Exynos
+ SoCs.
+
config USB_EHCI_MARVELL
bool "Support for Marvell on-chip EHCI USB controller"
depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-/* USB */
-#define CONFIG_USB_EHCI_EXYNOS
-
-#define CONFIG_USB_XHCI_EXYNOS
-
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#define CONFIG_LOWPOWER_FLAG 0x02020028
#define CONFIG_LOWPOWER_ADDR 0x0202002C
-#define CONFIG_USB_XHCI_EXYNOS
-
#endif /* __CONFIG_EXYNOS5420_H */
"kernel_addr_r=0x41000000\0" \
BOOTENV
-/* GPT */
-
-/* USB */
-#define CONFIG_USB_EHCI_EXYNOS
-
/*
* Supported Odroid boards: X3, U3
* TODO: Add Odroid X support
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-/* USB */
-#define CONFIG_USB_EHCI_EXYNOS
-
/* DFU */
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_SDRAM_BASE 0x20000000
-/* USB */
-#define CONFIG_USB_XHCI_EXYNOS
-
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */