fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by: Trung Tran <trung.tran@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id0408b3a560b25234886a9fa01c4ed248d1d1532

diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 696771f46c83015441215cadfb39e36986cc8b01..9aa144124b7129a48911b9465bc2fbe8e183fd04 100644 (file)
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -103,12 +103,15 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define PLAT_VERSAL_IPI_IRQ    62
+#define PLAT_VERSAL_NET_IPI_IRQ        89
+#define PLAT_VERSAL_IPI_IRQ    PLAT_VERSAL_NET_IPI_IRQ
 
 #define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \
        INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
                        GIC_INTR_CFG_LEVEL)
 
-#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp)
+#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) \
+       INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+                       GIC_INTR_CFG_EDGE), \
 
 #endif /* PLATFORM_DEF_H */