drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>  # mesa anvil & iris
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-5-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 38f7de7789144c8119f66c4451429a3f448cf42d..2efd2201359eaae8c969d4b3850ebcaf5f870244 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
                BIT(RCS0) | BIT(BCS0) |
                BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
                BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
-               BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+               BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
        .require_force_probe = 1,
 };
 
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
        .platform_engine_mask = \
                BIT(RCS0) | BIT(BCS0) | \
                BIT(VECS0) | BIT(VECS1) | \
-               BIT(VCS0) | BIT(VCS2)
+               BIT(VCS0) | BIT(VCS2) | \
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
 __maybe_unused
 static const struct intel_device_info dg2_info = {