drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards

[Why]
Support for DMUB only depends on support for DC. It doesn't use floating
point so we don't need to guard it by any specific DCN revision.

[How]
Drop the guards and cleanup the newlines around each one.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index fced39e229d55fd615486d548e274fed7bf6ea8b..313183b800328c11cb7c5ec8d25a362afbe7037c 100644 (file)
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -30,7 +30,6 @@ config DRM_AMD_DC_DCN2_1
        bool "DCN 2.1 family"
        depends on DRM_AMD_DC && X86
        depends on DRM_AMD_DC_DCN2_0
-       select DRM_AMD_DC_DMUB
        help
          Choose this option if you want to have
          Renoir support for display engine
@@ -53,11 +52,6 @@ config DRM_AMD_DC_HDCP
         if you want to support
         HDCP authentication
 
-config DRM_AMD_DC_DMUB
-        def_bool n
-        help
-          DMUB support for display engine
-
 config DEBUG_KERNEL_DC
        bool "Enable kgdb break in DC"
        depends on DRM_AMD_DC

diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
index 3c7332be4a89f82eb0dfd7766d792ad01ebc0693..2633de77de5e4fe4c4e76950f2fe66a2161cf8a4 100644 (file)
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -34,27 +34,21 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
+
 ifdef CONFIG_DRM_AMD_DC_HDCP
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
 endif
 
-ifdef CONFIG_DRM_AMD_DC_DMUB
-subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
-endif
-
 #TODO: remove when Timing Sync feature is complete
 subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
 
-DAL_LIBS = amdgpu_dm dc        modules/freesync modules/color modules/info_packet modules/power
+DAL_LIBS = amdgpu_dm dc        modules/freesync modules/color modules/info_packet modules/power dmub/src
 
 ifdef CONFIG_DRM_AMD_DC_HDCP
 DAL_LIBS += modules/hdcp
 endif
 
-ifdef CONFIG_DRM_AMD_DC_DMUB
-DAL_LIBS += dmub/src
-endif
-
 AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
 
 include $(AMD_DAL)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ee6ea333ba3daf1fe898a6a2d1132e9e7732890c..8e68fec5cc33c59aed8e63a5ed910662ae96b7d7 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -30,12 +30,10 @@
 #include "dc.h"
 #include "dc/inc/core_types.h"
 #include "dal_asic_id.h"
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 #include "dmub/inc/dmub_srv.h"
 #include "dc/inc/hw/dmcu.h"
 #include "dc/inc/hw/abm.h"
 #include "dc/dc_dmub_srv.h"
-#endif
 
 #include "vid.h"
 #include "amdgpu.h"
@@ -93,10 +91,9 @@
 #include "modules/power/power_helpers.h"
 #include "modules/inc/mod_info_packet.h"
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
-#endif
+
 #define FIRMWARE_RAVEN_DMCU            "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 
@@ -677,7 +674,6 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
        }
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 static int dm_dmub_hw_init(struct amdgpu_device *adev)
 {
        const unsigned int psp_header_bytes = 0x100;
@@ -816,16 +812,13 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
        return 0;
 }
 
-#endif
 static int amdgpu_dm_init(struct amdgpu_device *adev)
 {
        struct dc_init_data init_data;
 #ifdef CONFIG_DRM_AMD_DC_HDCP
        struct dc_callback_init init_params;
 #endif
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        int r;
-#endif
 
        adev->dm.ddev = adev->ddev;
        adev->dm.adev = adev;
@@ -902,14 +895,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 
        dc_hardware_init(adev->dm.dc);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        r = dm_dmub_hw_init(adev);
        if (r) {
                DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
                goto error;
        }
 
-#endif
        adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
        if (!adev->dm.freesync_module) {
                DRM_ERROR(
@@ -982,7 +973,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
        if (adev->dm.dc)
                dc_deinit_callbacks(adev->dm.dc);
 #endif
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (adev->dm.dc->ctx->dmub_srv) {
                dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
                adev->dm.dc->ctx->dmub_srv = NULL;
@@ -992,7 +982,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
                amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
                                      &adev->dm.dmub_bo_gpu_addr,
                                      &adev->dm.dmub_bo_cpu_addr);
-#endif
 
        /* DC Destroy TODO: Replace destroy DAL */
        if (adev->dm.dc)
@@ -1104,7 +1093,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        return 0;
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
 {
        struct amdgpu_device *adev = ctx;
@@ -1190,19 +1178,15 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
        return 0;
 }
 
-#endif
 static int dm_sw_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        int r;
 
        r = dm_dmub_sw_init(adev);
        if (r)
                return r;
 
-#endif
-
        return load_dmcu_fw(adev);
 }
 
@@ -1210,7 +1194,6 @@ static int dm_sw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (adev->dm.dmub_srv) {
                dmub_srv_destroy(adev->dm.dmub_srv);
                adev->dm.dmub_srv = NULL;
@@ -1221,7 +1204,6 @@ static int dm_sw_fini(void *handle)
                adev->dm.dmub_fw = NULL;
        }
 
-#endif
        if(adev->dm.fw_dmcu) {
                release_firmware(adev->dm.fw_dmcu);
                adev->dm.fw_dmcu = NULL;

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index c636a958e377363e18ecefec34d68c3c21e9da81..ab5da59aadc1cf2f7826ac08357abdfb39814d8a 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -57,10 +57,8 @@ struct amdgpu_device;
 struct drm_device;
 struct amdgpu_dm_irq_handler_data;
 struct dc;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 struct amdgpu_bo;
 struct dmub_srv;
-#endif
 
 struct common_irq_params {
        struct amdgpu_device *adev;
@@ -125,7 +123,6 @@ struct amdgpu_display_manager {
 
        struct dc *dc;
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        /**
         * @dmub_srv:
         *
@@ -170,7 +167,6 @@ struct amdgpu_display_manager {
         */
        uint32_t dmcub_fw_version;
 
-#endif
        /**
         * @cgs_device:
         *

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 6fe39f6392c770a8c0f03c6a45d2a4082dc43270..90482b158283e078899ac90c887bf859047f67f3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -70,9 +70,6 @@ AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
 AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
 AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
 
-ifdef CONFIG_DRM_AMD_DC_DMUB
 DC_DMUB += dc_dmub_srv.o
 AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
 AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB)
-endif
-

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index a3d890050e39837697435131acf469a5fb8af5ce..1836f16bb7fe010ce19d6b59e7addcba3daf4913 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -37,10 +37,8 @@
 #include "bios_parser_types_internal2.h"
 #include "amdgpu.h"
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 #include "dc_dmub_srv.h"
 #include "dc.h"
-#endif
 
 #define DC_LOGGER \
        bp->base.ctx->logger
@@ -107,7 +105,6 @@ static void init_dig_encoder_control(struct bios_parser *bp)
        }
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 static void encoder_control_dmcub(
                struct dc_dmub_srv *dmcub,
                struct dig_encoder_stream_setup_parameters_v1_5 *dig)
@@ -121,7 +118,7 @@ static void encoder_control_dmcub(
        dc_dmub_srv_cmd_execute(dmcub);
        dc_dmub_srv_wait_idle(dmcub);
 }
-#endif
+
 static enum bp_result encoder_control_digx_v1_5(
        struct bios_parser *bp,
        struct bp_encoder_control *cntl)
@@ -173,13 +170,12 @@ static enum bp_result encoder_control_digx_v1_5(
                default:
                        break;
                }
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
        if (bp->base.ctx->dc->ctx->dmub_srv &&
            bp->base.ctx->dc->debug.dmub_command_table) {
                encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
                return BP_RESULT_OK;
        }
-#endif
 
        if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
                result = BP_RESULT_OK;
@@ -216,7 +212,7 @@ static void init_transmitter_control(struct bios_parser *bp)
                break;
        }
 }
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
 static void transmitter_control_dmcub(
                struct dc_dmub_srv *dmcub,
                struct dig_transmitter_control_parameters_v1_6 *dig)
@@ -230,7 +226,7 @@ static void transmitter_control_dmcub(
        dc_dmub_srv_cmd_execute(dmcub);
        dc_dmub_srv_wait_idle(dmcub);
 }
-#endif
+
 static enum bp_result transmitter_control_v1_6(
        struct bios_parser *bp,
        struct bp_transmitter_control *cntl)
@@ -262,14 +258,11 @@ static enum bp_result transmitter_control_v1_6(
                __func__, ps.param.symclk_10khz);
        }
 
-
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (bp->base.ctx->dc->ctx->dmub_srv &&
            bp->base.ctx->dc->debug.dmub_command_table) {
                transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
                return BP_RESULT_OK;
        }
-#endif
 
 /*color_depth not used any more, driver has deep color factor in the Phyclk*/
        if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
@@ -303,7 +296,6 @@ static void init_set_pixel_clock(struct bios_parser *bp)
        }
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 static void set_pixel_clock_dmcub(
                struct dc_dmub_srv *dmcub,
                struct set_pixel_clock_parameter_v1_7 *clk)
@@ -317,7 +309,6 @@ static void set_pixel_clock_dmcub(
        dc_dmub_srv_cmd_execute(dmcub);
        dc_dmub_srv_wait_idle(dmcub);
 }
-#endif
 
 static enum bp_result set_pixel_clock_v7(
        struct bios_parser *bp,
@@ -393,13 +384,12 @@ static enum bp_result set_pixel_clock_v7(
                if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
                        clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
                if (bp->base.ctx->dc->ctx->dmub_srv &&
                    bp->base.ctx->dc->debug.dmub_command_table) {
                        set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
                        return BP_RESULT_OK;
                }
-#endif
+
                if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
                        result = BP_RESULT_OK;
        }
@@ -653,7 +643,7 @@ static void init_enable_disp_power_gating(
                break;
        }
 }
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
 static void enable_disp_power_gating_dmcub(
        struct dc_dmub_srv *dmcub,
        struct enable_disp_power_gating_parameters_v2_1 *pwr)
@@ -667,7 +657,7 @@ static void enable_disp_power_gating_dmcub(
        dc_dmub_srv_cmd_execute(dmcub);
        dc_dmub_srv_wait_idle(dmcub);
 }
-#endif
+
 static enum bp_result enable_disp_power_gating_v2_1(
        struct bios_parser *bp,
        enum controller_id crtc_id,
@@ -687,14 +677,13 @@ static enum bp_result enable_disp_power_gating_v2_1(
        ps.param.enable =
                bp->cmd_helper->disp_power_gating_action_to_atom(action);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (bp->base.ctx->dc->ctx->dmub_srv &&
            bp->base.ctx->dc->debug.dmub_command_table) {
                enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
                                               &ps.param);
                return BP_RESULT_OK;
        }
-#endif
+
        if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
                result = BP_RESULT_OK;
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2bf4da41577a931f4bcbc7bd1d55522b347690d6..0a5f91ab4652602158a736dc59339229f5dc54fa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -58,10 +58,7 @@
 #include "hubp.h"
 
 #include "dc_link_dp.h"
-
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 #include "dc_dmub_srv.h"
-#endif
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 #include "dsc.h"
@@ -2410,10 +2407,9 @@ void dc_set_power_state(
        switch (power_state) {
        case DC_ACPI_CM_POWER_STATE_D0:
                dc_resource_state_construct(dc, dc->current_state);
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
                if (dc->ctx->dmub_srv)
                        dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
-#endif
 
                dc->hwss.init_hw(dc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 33828f03fe9efe0feff56fec474c74056c5d7505..30a2783881d9efe0684d7246ea023f95548e8ca3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -112,9 +112,7 @@ struct dc_caps {
        bool disable_dp_clk_share;
        bool psp_setup_panel_mode;
        bool extended_aux_timeout_support;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        bool dmcub_support;
-#endif
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
        bool hw_3d_lut;
 #endif
@@ -404,11 +402,9 @@ struct dc_debug_options {
        unsigned int force_odm_combine; //bit vector based on otg inst
        unsigned int force_fclk_khz;
        bool disable_tri_buf;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        bool dmub_offload_enabled;
        bool dmcub_emulation;
        bool dmub_command_table; /* for testing only */
-#endif
        struct dc_bw_validation_profile bw_val_profile;
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
        bool disable_fec;
@@ -566,10 +562,9 @@ struct dc_init_data {
        struct dc_bios *vbios_override;
        enum dce_environment dce_environment;
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        struct dmub_offload_funcs *dmub_if;
        struct dc_reg_helper_state *dmub_offload;
-#endif
+
        struct dc_config flags;
        uint32_t log_mask;
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 59b4bbefb7a44d3c62de1a35b4684dc5dbb9ef95..8da4576e2908de4b219224afe4a2ba57961697f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -32,7 +32,6 @@
 #include "dm_services.h"
 #include <stdarg.h>
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 #include "dc.h"
 #include "dc_dmub_srv.h"
 
@@ -100,7 +99,6 @@ static inline void submit_dmub_reg_wait(
 
        ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
 }
-#endif
 
 struct dc_reg_value_masks {
        uint32_t value;
@@ -147,7 +145,6 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
        }
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 static void dmub_flush_buffer_execute(
                struct dc_reg_helper_state *offload,
                const struct dc_context *ctx)
@@ -239,8 +236,6 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
        cmd_buf->reg_wait.time_out_us = time_out_us;
 }
 
-#endif
-
 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
                uint32_t addr, int n,
                uint8_t shift1, uint32_t mask1, uint32_t field_value1,
@@ -257,12 +252,10 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
 
        va_end(ap);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (ctx->dmub_srv &&
            ctx->dmub_srv->reg_helper_offload.gather_in_progress)
                return dmub_reg_value_pack(ctx, addr, &field_value_mask);
                /* todo: return void so we can decouple code running in driver from register states */
-#endif
 
        /* mmio write directly */
        reg_val = dm_read_reg(ctx, addr);
@@ -289,13 +282,13 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
 
        /* mmio write directly */
        reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
        if (ctx->dmub_srv &&
            ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
                return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
                /* todo: return void so we can decouple code running in driver from register states */
        }
-#endif
+
        dm_write_reg(ctx, addr, reg_val);
        return reg_val;
 }
@@ -313,14 +306,12 @@ uint32_t dm_read_reg_func(
        }
 #endif
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (ctx->dmub_srv &&
            ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
            !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
                ASSERT(false);
                return 0;
        }
-#endif
 
        value = cgs_read_register(ctx->cgs_device, address);
        trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
@@ -487,14 +478,12 @@ void generic_reg_wait(const struct dc_context *ctx,
        uint32_t reg_val;
        int i;
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        if (ctx->dmub_srv &&
            ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
                dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
                                delay_between_poll_us * time_out_num_tries);
                return;
        }
-#endif
 
        /* something is terribly wrong if time out is > 200ms. (5Hz) */
        ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
@@ -542,13 +531,12 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
                uint32_t index)
 {
        uint32_t value = 0;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
        // when reg read, there should not be any offload.
        if (ctx->dmub_srv &&
            ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
                ASSERT(false);
        }
-#endif
 
        dm_write_reg(ctx, addr_index, index);
        value = dm_read_reg(ctx, addr_data);
@@ -587,7 +575,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
        return reg_val;
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 void reg_sequence_start_gather(const struct dc_context *ctx)
 {
        /* if reg sequence is supported and enabled, set flag to
@@ -652,6 +639,3 @@ void reg_sequence_wait_done(const struct dc_context *ctx)
                dc_dmub_srv_wait_idle(ctx->dmub_srv);
        }
 }
-
-
-#endif

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index fb70ed9b351fe79b7f4e0c5f5eb89065f1cf7603..7ab7644458e7c050a6c785c46d8388982243ad1a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -48,9 +48,7 @@ struct dc_stream_state;
 struct dc_link;
 struct dc_sink;
 struct dal;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 struct dc_dmub_srv;
-#endif
 
 /********************************
  * Environment definitions
@@ -112,9 +110,8 @@ struct dc_context {
        uint32_t dc_sink_id_count;
        uint32_t dc_stream_id_count;
        uint64_t fbc_gpu_addr;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        struct dc_dmub_srv *dmub_srv;
-#endif
+
 #ifdef CONFIG_DRM_AMD_DC_HDCP
        struct cp_psp cp_psp;
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 41a0e53d2ba4f8b3a986b10a4755831dd89ac87b..6f1a312c6a5ada337dbc0e93c7b58d059ea530f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -352,9 +352,8 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
        uint32_t i;
        struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        REG_SEQ_START();
-#endif
+
        for (i = 0 ; i < num; i++) {
                REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
                REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
@@ -633,10 +632,9 @@ void dpp1_set_degamma(
                BREAK_TO_DEBUGGER();
                break;
        }
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
        REG_SEQ_SUBMIT();
        REG_SEQ_WAIT_DONE();
-#endif
 }
 
 void dpp1_degamma_ram_select(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 8710f3ac2abf6ae6b8f31e0c9cecc99d655c2e35..30c025918568a2aea8033247507174b5a4c12e86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -457,18 +457,15 @@ static bool optc1_enable_crtc(struct timing_generator *optc)
        REG_UPDATE(CONTROL,
                        VTG0_ENABLE, 1);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        REG_SEQ_START();
-#endif
+
        /* Enable CRTC */
        REG_UPDATE_2(OTG_CONTROL,
                        OTG_DISABLE_POINT_CNTL, 3,
                        OTG_MASTER_EN, 1);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        REG_SEQ_SUBMIT();
        REG_SEQ_WAIT_DONE();
-#endif
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 2417d933ef2b22861fc8235ff1cf425c67d3ebee..f90031ed58a640c344d6b2489057fe05ec9eb768 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -345,10 +345,8 @@ static void mpc20_program_ogam_pwl(
        uint32_t i;
        struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        PERF_TRACE();
        REG_SEQ_START();
-#endif
 
        for (i = 0 ; i < num; i++) {
                REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
@@ -468,12 +466,11 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
                ASSERT(!mpc_disabled);
                ASSERT(!mpc_idle);
        }
-#ifdef CONFIG_DRM_AMD_DC_DMUB
+
        REG_SEQ_SUBMIT();
        PERF_TRACE();
        REG_SEQ_WAIT_DONE();
        PERF_TRACE();
-#endif
 }
 
 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index eb7ce4a5cbac2f1a6954ccc47baaaa7d99d67306..6fcfc0a643c0d3255b10a80af6df6d36a32320e1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1678,9 +1678,7 @@ static bool construct(
        dc->caps.post_blend_color_processing = true;
        dc->caps.force_dp_tps4_for_cp2520 = true;
        dc->caps.extended_aux_timeout_support = true;
-#ifdef CONFIG_DRM_AMD_DC_DMUB
        dc->caps.dmcub_support = true;
-#endif
 
        if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
                dc->debug = debug_defaults_drv;

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 0a3891edfd9457ce1c17f6f7d31ba0c09424900e..968ff1fef486d76274fed8973b5b74844c85df9c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -40,11 +40,9 @@
 
 #undef DEPRECATED
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 struct dmub_srv;
 struct dc_dmub_srv;
 
-#endif
 irq_handler_idx dm_register_interrupt(
        struct dc_context *ctx,
        struct dc_interrupt_params *int_params,
@@ -144,14 +142,12 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
                uint32_t addr, int n,
                uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
 
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
 
 void reg_sequence_start_gather(const struct dc_context *ctx);
 void reg_sequence_start_execute(const struct dc_context *ctx);
 void reg_sequence_wait_done(const struct dc_context *ctx);
-#endif
 
 #define FD(reg_field)  reg_field ## __SHIFT, \
                                                reg_field ## _MASK

diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index a9a9657c095a15f7bf8efd91c1a9f97e4be2befe..47e307388581a88424427101ca8f3adfb5df6d68 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -485,8 +485,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
                uint8_t shift1, uint32_t mask1, uint32_t field_value1,
                ...);
 
-
-#ifdef CONFIG_DRM_AMD_DC_DMUB
 /* register offload macros
  *
  * instead of MMIO to register directly, in some cases we want
@@ -505,6 +503,5 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
 /* wait for the last REG_SEQ_SUBMIT to finish */
 #define REG_SEQ_WAIT_DONE() \
        reg_sequence_wait_done(CTX)
-#endif
 
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */

diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index f3b844f474fde0ff8b7c725c8ed5aa53cde8d620..e08dfeea24b06ce7f6af6c84e269866fa3c9ab1d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -20,10 +20,8 @@
 # OTHER DEALINGS IN THE SOFTWARE.
 #
 
-ifdef CONFIG_DRM_AMD_DC_DMUB
 DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_DMUB)
-endif