fix(versal): sync location based on IPI_ID macros

IPI_ID_* macros available at include/plat_ipi.h are using PMC/APU/RPU0..
order which is not how versal_ipi_table array is composed. That's why
swap APU and PMC to follow the same order as is described by macros.

Change-Id: Ieaa3a967650e298e7cff45fafde0df96294c09fe
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index d821929a88705bae965cb0efe18edf8a41aafeaa..75d4c1436c9d3cd2b607884fbaf029f618497d43 100644 (file)
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -20,16 +20,16 @@
 
 /* versal ipi configuration table */
 static const struct ipi_config versal_ipi_table[] = {
-       /* A72 IPI */
-       [IPI_ID_APU] = {
-               .ipi_bit_mask = IPI0_TRIG_BIT,
+       /* PMC IPI */
+       [IPI_ID_PMC] = {
+               .ipi_bit_mask = PMC_IPI_TRIG_BIT,
                .ipi_reg_base = IPI0_REG_BASE,
                .secure_only = 0U,
        },
 
-       /* PMC IPI */
-       [IPI_ID_PMC] = {
-               .ipi_bit_mask = PMC_IPI_TRIG_BIT,
+       /* A72 IPI */
+       [IPI_ID_APU] = {
+               .ipi_bit_mask = IPI0_TRIG_BIT,
                .ipi_reg_base = IPI0_REG_BASE,
                .secure_only = 0U,
        },