drm/i915: Extend QGV point restrict mask to 0x3

According to BSpec there is now also a code 0x02,
which corresponds to QGV point being rejected,
this code so lets extend mask to check this.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210531064845.4389-1-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e13e913fb5c49d82632915dc6e2dd3de98872b46..5d670c54e3afd4252fd35038465d6cec881a6bfa 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9375,7 +9375,7 @@ enum {
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)        (((point) << 16) | (0x1 << 8))
 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG      0xe
 #define     ICL_PCODE_POINTS_RESTRICTED                0x0
-#define     ICL_PCODE_POINTS_RESTRICTED_MASK   0x1
+#define     ICL_PCODE_POINTS_RESTRICTED_MASK   0x3
 #define   GEN6_PCODE_READ_D_COMP               0x10
 #define   GEN6_PCODE_WRITE_D_COMP              0x11
 #define   ICL_PCODE_EXIT_TCCOLD                        0x12