clk: at91: sama7g5: register cpu clock

Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 927eb3b2b126d36e2a6898df2df6d59990fd13bb..a6e20b35960e035d4b8c7324d807e3665001a5d7 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
        if (IS_ERR(regmap))
                return;
 
-       sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
+       sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
                                        nck(sama7g5_systemck),
                                        nck(sama7g5_periphck),
                                        nck(sama7g5_gck), 8);
@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
                }
        }
 
-       parent_names[0] = md_slck_name;
-       parent_names[1] = "mainck";
-       parent_names[2] = "cpupll_divpmcck";
-       parent_names[3] = "syspll_divpmcck";
-       hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
+       parent_names[0] = "cpupll_divpmcck";
+       hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
                                           &mck0_layout, &mck0_characteristics,
                                           &pmc_mck0_lock,
                                           CLK_SET_RATE_PARENT, 0);
        if (IS_ERR(hw))
                goto err_free;
 
-       hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
+       sama7g5_pmc->chws[PMC_CPU] = hw;
+
+       hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
                                          &mck0_layout, &mck0_characteristics,
                                          &pmc_mck0_lock, 0);
        if (IS_ERR(hw))

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index fab313f62e8f59de326cf1059aaed798a0ded8f2..98e1b2ab6403934920c89fe1219205abce10e10e 100644 (file)
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -34,6 +34,7 @@
 #define PMC_AUDIOPMCPLL                (PMC_MAIN + 6)
 #define PMC_AUDIOIOPLL         (PMC_MAIN + 7)
 #define PMC_ETHPLL             (PMC_MAIN + 8)
+#define PMC_CPU                        (PMC_MAIN + 9)
 
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS         0               /* MOSCS Flag */