bx lr
ENDPROC(_nonsec_init)
-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
/* void __weak smp_waitloop(unsigned previous_address); */
WEAK(smp_waitloop)
wfi
- ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
+ ldr r1, =CFG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
rev r1, r1
}
#endif
-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
- writel(addr, CONFIG_SMP_PEN_ADDR);
+ writel(addr, CFG_SMP_PEN_ADDR);
/* make sure this write is really executed */
__asm__ volatile ("dsb\n");
/* Miscellaneous configurable options */
-#define CONFIG_SMP_PEN_ADDR 0x02020000
+#define CFG_SMP_PEN_ADDR 0x02020000
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000
{1, {I2C_NULL_HOP} }, \
}
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CFG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CFG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
* MMC
*/
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CFG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
/* GPIO */
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CFG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256