riscv: Rename Andes PLIC to PLICSW

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8f9578171d35ea3cafcef168ab615628f70dbe53..4d64e9be3f2fb9603aa2908e38bf0660ff5caaf5 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -199,7 +199,7 @@ config SIFIVE_CACHE
        help
          This enables the operations to configure SiFive cache
 
-config ANDES_PLIC
+config ANDES_PLICSW
        bool
        depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
@@ -207,8 +207,8 @@ config ANDES_PLIC
        select SPL_REGMAP if SPL
        select SPL_SYSCON if SPL
        help
-         The Andes PLIC block holds memory-mapped claim and pending registers
-         associated with software interrupt.
+         The Andes PLICSW block holds memory-mapped claim and pending
+         registers associated with software interrupt.
 
 config SMP
        bool "Symmetric Multi-Processing"

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 941d963ece48ef4720de32c4a14cff26eeae438b..4a7295d30c5fd1cf80ee5aae92f43933b0be166b 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,7 +4,7 @@ config RISCV_NDS
        imply CPU
        imply CPU_RISCV
        imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-       imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+       imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply SPL_CPU
        imply SPL_OPENSBI

diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index 0d4201cfae9fa7e779727453a60f731252d0cc44..7011f598316bb69ad7b8a82d1fa3c29847a1a864 100644 (file)
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -36,7 +36,7 @@
        soc {
                u-boot,dm-spl;
 
-               plic1: interrupt-controller@e6400000 {
+               plicsw: interrupt-controller@e6400000 {
                        u-boot,dm-spl;
                };
 

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 083f676333de1f41f7e2633a07686968d535de94..96ef8bd8ddbc87e5847d52af646c4c7bdc40e393 100644 (file)
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -146,8 +146,8 @@
                                &CPU3_intc 11 &CPU3_intc 9>;
                };
 
-               plic1: interrupt-controller@e6400000 {
-                       compatible = "riscv,plic1";
+               plicsw: interrupt-controller@e6400000 {
+                       compatible = "andestech,plicsw";
                        #interrupt-cells = <1>;
                        interrupt-controller;
                        reg = <0xe6400000 0x400000>;
@@ -159,7 +159,7 @@
                };
 
                plmt0@e6000000 {
-                       compatible = "riscv,plmt0";
+                       compatible = "andestech,plmt0";
                        interrupts-extended = <&CPU0_intc 7
                                &CPU1_intc 7
                                &CPU2_intc 7

diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 74cff9122d4df8e1f6fa4c03946ebc170ba12532..cddbaec98ad55bb944accac6e21c68c827c82a4f 100644 (file)
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -146,8 +146,8 @@
                                &CPU3_intc 11 &CPU3_intc 9>;
                };
 
-               plic1: interrupt-controller@e6400000 {
-                       compatible = "riscv,plic1";
+               plicsw: interrupt-controller@e6400000 {
+                       compatible = "andestech,plicsw";
                        #interrupt-cells = <2>;
                        interrupt-controller;
                        reg = <0x0 0xe6400000 0x0 0x400000>;
@@ -159,7 +159,7 @@
                };
 
                plmt0@e6000000 {
-                       compatible = "riscv,plmt0";
+                       compatible = "andestech,plmt0";
                        interrupts-extended = <&CPU0_intc 7
                                &CPU1_intc 7
                                &CPU2_intc 7

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 858594a1911f68b35ecee54930c5d29303e8cfe8..6fdc86dd8b1d13c546ba4ee272bd46a72715733c 100644 (file)
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,8 +21,8 @@ struct arch_global_data {
 #if CONFIG_IS_ENABLED(SIFIVE_CLINT)
        void __iomem *clint;    /* clint base address */
 #endif
-#ifdef CONFIG_ANDES_PLIC
-       void __iomem *plic;     /* plic base address */
+#ifdef CONFIG_ANDES_PLICSW
+       void __iomem *plicsw;   /* plic base address */
 #endif
 #if CONFIG_IS_ENABLED(SMP)
        struct ipi_data ipi[CONFIG_NR_CPUS];

diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index c3629e4b53d6a16156a5df6ef8929787e8dcabe8..f2b37975f37d989e9f833b09b7390dacd7904aa6 100644 (file)
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -13,7 +13,7 @@
 enum {
        RISCV_NONE,
        RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
-       RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
+       RISCV_SYSCON_PLICSW,    /* Andes PLICSW */
 };
 
 #endif /* _ASM_SYSCON_H */

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 06020fcc2ad400a10947ac24319f6728cdbc43d4..d6a8ae97284ee4e0ae5a9afbe8c96e6204ad5a90 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,7 +13,7 @@ obj-y += cache.o
 obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
-obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
 else
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
deleted file mode 100644 (file)
index 1eabcac..0000000
--- a/arch/riscv/lib/andes_plic.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019, Rick Chen <rick@andestech.com>
- *
- * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
- * The PLIC block holds memory-mapped claim and pending registers
- * associated with software interrupt.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
-#include <dm/uclass-internal.h>
-#include <regmap.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/syscon.h>
-#include <cpu.h>
-#include <linux/err.h>
-
-/* pending register */
-#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
-/* enable register */
-#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
-/* claim register */
-#define CLAIM_REG(base, hart)  ((ulong)(base) + 0x200004 + (hart) * 0x1000)
-
-#define ENABLE_HART_IPI         (0x01010101)
-#define SEND_IPI_TO_HART(hart)  (0x1 << (hart))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int enable_ipi(int hart)
-{
-       unsigned int en;
-
-       en = ENABLE_HART_IPI << hart;
-       writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
-       writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
-
-       return 0;
-}
-
-int riscv_init_ipi(void)
-{
-       int ret;
-       long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
-       ofnode node;
-       struct udevice *dev;
-       u32 reg;
-
-       if (IS_ERR(base))
-               return PTR_ERR(base);
-       gd->arch.plic = base;
-
-       ret = uclass_find_first_device(UCLASS_CPU, &dev);
-       if (ret)
-               return ret;
-       else if (!dev)
-               return -ENODEV;
-
-       ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
-               const char *device_type;
-
-               device_type = ofnode_read_string(node, "device_type");
-               if (!device_type)
-                       continue;
-
-               if (strcmp(device_type, "cpu"))
-                       continue;
-
-               /* skip if hart is marked as not available */
-               if (!ofnode_is_enabled(node))
-                       continue;
-
-               /* read hart ID of CPU */
-               ret = ofnode_read_u32(node, "reg", &reg);
-               if (ret == 0)
-                       enable_ipi(reg);
-       }
-
-       return 0;
-}
-
-int riscv_send_ipi(int hart)
-{
-       unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
-
-       writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
-                               gd->arch.boot_hart));
-
-       return 0;
-}
-
-int riscv_clear_ipi(int hart)
-{
-       u32 source_id;
-
-       source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
-       writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
-
-       return 0;
-}
-
-int riscv_get_ipi(int hart, int *pending)
-{
-       unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
-
-       *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
-                                                    gd->arch.boot_hart));
-       *pending = !!(*pending & ipi);
-
-       return 0;
-}
-
-static const struct udevice_id andes_plic_ids[] = {
-       { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
-       { }
-};
-
-U_BOOT_DRIVER(andes_plic) = {
-       .name           = "andes_plic",
-       .id             = UCLASS_SYSCON,
-       .of_match       = andes_plic_ids,
-       .flags          = DM_FLAG_PRE_RELOC,
-};

diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
new file mode 100644 (file)
index 0000000..324eb44
--- /dev/null
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <cpu.h>
+#include <linux/err.h>
+
+/* pending register */
+#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
+/* enable register */
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart)  ((ulong)(base) + 0x200004 + (hart) * 0x1000)
+
+#define ENABLE_HART_IPI         (0x01010101)
+#define SEND_IPI_TO_HART(hart)  (0x1 << (hart))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int enable_ipi(int hart)
+{
+       unsigned int en;
+
+       en = ENABLE_HART_IPI << hart;
+       writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
+       writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
+
+       return 0;
+}
+
+int riscv_init_ipi(void)
+{
+       int ret;
+       long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
+       ofnode node;
+       struct udevice *dev;
+       u32 reg;
+
+       if (IS_ERR(base))
+               return PTR_ERR(base);
+       gd->arch.plicsw = base;
+
+       ret = uclass_find_first_device(UCLASS_CPU, &dev);
+       if (ret)
+               return ret;
+       else if (!dev)
+               return -ENODEV;
+
+       ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+               const char *device_type;
+
+               device_type = ofnode_read_string(node, "device_type");
+               if (!device_type)
+                       continue;
+
+               if (strcmp(device_type, "cpu"))
+                       continue;
+
+               /* skip if hart is marked as not available */
+               if (!ofnode_is_enabled(node))
+                       continue;
+
+               /* read hart ID of CPU */
+               ret = ofnode_read_u32(node, "reg", &reg);
+               if (ret == 0)
+                       enable_ipi(reg);
+       }
+
+       return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+       unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
+       writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
+                               gd->arch.boot_hart));
+
+       return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+       u32 source_id;
+
+       source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
+       writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
+
+       return 0;
+}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+       unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
+       *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
+                                                    gd->arch.boot_hart));
+       *pending = !!(*pending & ipi);
+
+       return 0;
+}
+
+static const struct udevice_id andes_plicsw_ids[] = {
+       { .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
+       { }
+};
+
+U_BOOT_DRIVER(andes_plicsw) = {
+       .name           = "andes_plicsw",
+       .id             = UCLASS_SYSCON,
+       .of_match       = andes_plicsw_ids,
+       .flags          = DM_FLAG_PRE_RELOC,
+};

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index a3797b22c74c4b3198a0c270ed48daabc97a3ee5..42dd4b6231764fba87c06c0ab4d82cab3654260b 100644 (file)
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -56,7 +56,7 @@ static int andes_plmt_probe(struct udevice *dev)
 }
 
 static const struct udevice_id andes_plmt_ids[] = {
-       { .compatible = "riscv,plmt0" },
+       { .compatible = "andestech,plmt0" },
        { }
 };