drm/dp/dsc: Add Support for all BPCs supported by TGL

DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.

v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)

v3: Use values directly instead of accessing the defines
everytime for min and max DSC BPC.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190820223059.18052-1-anusha.srivatsa@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 921ad0a2f7ba7c743bea90622216d019846a6f22..23908da1cd5da37629cf21469c99bf9bb72da969 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -70,8 +70,6 @@
 
 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER     61440
-#define DP_DSC_MIN_SUPPORTED_BPC               8
-#define DP_DSC_MAX_SUPPORTED_BPC               10
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE                 2720000
@@ -1915,11 +1913,17 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
        if (!intel_dp_supports_dsc(intel_dp, pipe_config))
                return -EINVAL;
 
-       dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
-                           conn_state->max_requested_bpc);
+       /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+       if (INTEL_GEN(dev_priv) >= 12)
+               dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+       else
+               dsc_max_bpc = min_t(u8, 10,
+                                   conn_state->max_requested_bpc);
 
        pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
-       if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
+
+       /* Min Input BPC for ICL+ is 8 */
+       if (pipe_bpp < 8 * 3) {
                DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
                return -EINVAL;
        }