r8152: disable DelayPhyPwrChg

When enabling this, the device would wait an internal signal which
wouldn't be triggered. Then, the device couldn't enter P3 mode, so
the power consumption is increased.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index c037fc7adcea97e717246b9569d93c3b1d244a1e..3f425f974d03cfaf311d5bc2c21bac0599b488a8 100644 (file)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -31,7 +31,7 @@
 #define NETNEXT_VERSION                "11"
 
 /* Information for net */
-#define NET_VERSION            "10"
+#define NET_VERSION            "11"
 
 #define DRIVER_VERSION         "v1." NETNEXT_VERSION "." NET_VERSION
 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
@@ -109,6 +109,7 @@
 #define PLA_BP_EN              0xfc38
 
 #define USB_USB2PHY            0xb41e
+#define USB_SSPHYLINK1         0xb426
 #define USB_SSPHYLINK2         0xb428
 #define USB_U2P3_CTRL          0xb460
 #define USB_CSR_DUMMY1         0xb464
@@ -384,6 +385,9 @@
 #define USB2PHY_SUSPEND                0x0001
 #define USB2PHY_L1             0x0002
 
+/* USB_SSPHYLINK1 */
+#define DELAY_PHY_PWR_CHG      BIT(1)
+
 /* USB_SSPHYLINK2 */
 #define pwd_dn_scale_mask      0x3ffe
 #define pwd_dn_scale(x)                ((x) << 1)
@@ -4994,6 +4998,10 @@ static void rtl8153_up(struct r8152 *tp)
        ocp_data &= ~LANWAKE_PIN;
        ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
 
+       ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
+       ocp_data &= ~DELAY_PHY_PWR_CHG;
+       ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
+
        r8153_aldps_en(tp, true);
 
        switch (tp->version) {