drm/amd/powerplay: Followup fixes to mc_reg_address

This is a followup to:
drm/amd/powerplay: Fix buffer overflows with mc_reg_address

Rework *_set_mc_special_registers for the other architectures to
use the same logic as the first patch. This allows the last entry
of the array to be filled without an error message for example.
This doesn't fix any known problems, perhaps avoided by luck.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 51fd0c9a20a5b7a1b08d7e0d65211a17bb86c8fd..299cb3161b2cc641751798895c0d3bb8b9616f11 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -5845,9 +5845,9 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
                                        ((temp_reg & 0xffff0000)) |
                                        ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
                        j++;
+
                        if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
                                return -EINVAL;
-
                        temp_reg = RREG32(MC_PMG_CMD_MRS);
                        table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
                        table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
@@ -5859,18 +5859,16 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
                                        table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
                        }
                        j++;
-                       if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
-                               return -EINVAL;
 
                        if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
+                               if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+                                       return -EINVAL;
                                table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
                                table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
                                for (k = 0; k < table->num_entries; k++)
                                        table->mc_reg_table_entry[k].mc_data[j] =
                                                (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
                                j++;
-                               if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
-                                       return -EINVAL;
                        }
                        break;
                case MC_SEQ_RESERVE_M:
@@ -5882,8 +5880,6 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
                                        (temp_reg & 0xffff0000) |
                                        (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
                        j++;
-                       if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
-                               return -EINVAL;
                        break;
                default:
                        break;

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index ed4b37e566a3be33f337dccc9c4b18621118bc19..c36f00ef46f3955b904cfbf0f73ab98455f67f43 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -2600,9 +2600,9 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                        ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
                        }
                        j++;
+
                        PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
                                "Invalid VramInfo table.", return -EINVAL);
-
                        temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
                        table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
                        table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -2615,10 +2615,10 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                        table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
                        }
                        j++;
-                       PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                               "Invalid VramInfo table.", return -EINVAL);
 
-                       if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+                       if (!data->is_memory_gddr5) {
+                               PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+                                       "Invalid VramInfo table.", return -EINVAL);
                                table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
                                table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
                                for (k = 0; k < table->num_entries; k++) {
@@ -2626,8 +2626,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                                (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
                                }
                                j++;
-                               PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                                       "Invalid VramInfo table.", return -EINVAL);
                        }
 
                        break;
@@ -2642,8 +2640,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                        (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
                        }
                        j++;
-                       PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                               "Invalid VramInfo table.", return -EINVAL);
                        break;
 
                default:

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 2ff682d44e8cdf38fb2662dde94c149c000af213..d62078681cae9d72d0414b48894f7532dfd16182 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -2549,9 +2549,9 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                        ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
                        }
                        j++;
+
                        PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
                                "Invalid VramInfo table.", return -EINVAL);
-
                        temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
                        table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
                        table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
@@ -2565,10 +2565,10 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                }
                        }
                        j++;
-                       PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                               "Invalid VramInfo table.", return -EINVAL);
 
-                       if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+                       if (!data->is_memory_gddr5) {
+                               PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+                                       "Invalid VramInfo table.", return -EINVAL);
                                table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
                                table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
                                for (k = 0; k < table->num_entries; k++) {
@@ -2576,8 +2576,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                                (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
                                }
                                j++;
-                               PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                                       "Invalid VramInfo table.", return -EINVAL);
                        }
 
                        break;
@@ -2592,8 +2590,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
                                        (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
                        }
                        j++;
-                       PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-                               "Invalid VramInfo table.", return -EINVAL);
                        break;
 
                default: