net/mlx5: Add bits and fields to support enhanced CQE compression

Expose ifc bits and add needed structure fields and methods to
support enhanced CQE compression feature.
The enhanced CQE compression feature improves cpu utiliziation with
better packet latency from nic to host.

Signed-off-by: Ofer Levi <oferle@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 95a4fa0fd40a8ac55c7d9de69b6a4f9b1a59305a..b5f58fd37a0f75905a86a6253861e1bd05bfb9e7 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -822,7 +822,10 @@ struct mlx5_cqe64 {
        __be32          timestamp_l;
        __be32          sop_drop_qpn;
        __be16          wqe_counter;
-       u8              signature;
+       union {
+               u8      signature;
+               u8      validity_iteration_count;
+       };
        u8              op_own;
 };
 
@@ -854,6 +857,11 @@ enum {
        MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
 };
 
+enum {
+       MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
+       MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
+};
+
 #define MLX5_MINI_CQE_ARRAY_SIZE 8
 
 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
@@ -866,6 +874,12 @@ static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
        return cqe->op_own >> 4;
 }
 
+static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
+{
+       /* num_of_mini_cqes is zero based */
+       return get_cqe_opcode(cqe) + 1;
+}
+
 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 {
        return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index f678ad88a7d5f988156b434a8779ee86003f8956..8e87eb47f9dce9b709f2c8bc9bd017c35b1bca60 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1739,7 +1739,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_dci_errored_streams[0x5];
        u8         reserved_at_598[0x8];
 
-       u8         reserved_at_5a0[0x13];
+       u8         reserved_at_5a0[0x10];
+       u8         enhanced_cqe_compression[0x1];
+       u8         reserved_at_5b1[0x2];
        u8         log_max_dek[0x5];
        u8         reserved_at_5b8[0x4];
        u8         mini_cqe_resp_stride_index[0x1];
@@ -4139,7 +4141,8 @@ struct mlx5_ifc_cqc_bits {
        u8         cqe_comp_en[0x1];
        u8         mini_cqe_res_format[0x2];
        u8         st[0x4];
-       u8         reserved_at_18[0x8];
+       u8         reserved_at_18[0x6];
+       u8         cqe_compression_layout[0x2];
 
        u8         reserved_at_20[0x20];