fix(versal-net): resolve misra 10.6 warnings

Fix below MISRA violation from versal_net_def.h:
 - MISRA Violation: MISRA-C:2012 R.10.6
  - The value of a composite expression shall not be assigned to an
    object with wider essential type

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I74f8e5d63523f33d245a21f8e4f04d30e40b05e7

diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index 8cb5bf3a3ab9d39064eb3fe213d7bad8638bdd61..45e240e710aa65bcacca07448d42cdaa3657dae3 100644 (file)
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -53,9 +53,9 @@
 
 #define PSX_CRF_RST_TIMESTAMP_OFFSET   U(0x33C)
 
-#define APU_PCLI                       U(0xECB10000)
-#define APU_PCLI_CPU_STEP              U(0x30)
-#define APU_PCLI_CLUSTER_CPU_STEP      (4U * APU_PCLI_CPU_STEP)
+#define APU_PCLI                       (0xECB10000ULL)
+#define APU_PCLI_CPU_STEP              (0x30ULL)
+#define APU_PCLI_CLUSTER_CPU_STEP      (4ULL * APU_PCLI_CPU_STEP)
 #define APU_PCLI_CLUSTER_OFFSET                U(0x8000)
 #define APU_PCLI_CLUSTER_STEP          U(0x1000)
 #define PCLI_PREQ_OFFSET               U(0x4)
@@ -67,13 +67,13 @@
 /* Firmware Image Package */
 #define VERSAL_NET_PRIMARY_CPU         U(0)
 
-#define CORE_0_IEN_POWER_OFFSET                        (0x00000018U)
+#define CORE_0_IEN_POWER_OFFSET                        (0x00000018ULL)
 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id)  (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
-                                                (0x30 * cpu_id)))
+                                                (APU_PCLI_CPU_STEP * cpu_id)))
 #define APU_PCIL_CORE_X_IEN_POWER_MASK         (0x00000001U)
-#define CORE_0_IDS_POWER_OFFSET                        (0x0000001CU)
+#define CORE_0_IDS_POWER_OFFSET                        (0x0000001CULL)
 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id)  (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
-                                                (0x30 * cpu_id)))
+                                                (APU_PCLI_CPU_STEP * cpu_id)))
 #define APU_PCIL_CORE_X_IDS_POWER_MASK         (0x00000001U)
 #define CORE_PWRDN_EN_BIT_MASK                 (0x1U)