i2c: i801: convert to use common P2SB accessor

Since we have a common P2SB accessor in tree we may use it instead of
open coded variants.

Replace custom code by p2sb_bar() call.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Henning Schild <henning.schild@siemens.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a1bae59208e346572063dc8a16fe8b9c89ecf583..4d0a195ca3ef7d7f16e7d4aa806bf19f2a1760ce 100644 (file)
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -108,6 +108,7 @@ config I2C_HIX5HD2
 config I2C_I801
        tristate "Intel 82801 (ICH/PCH)"
        depends on PCI
+       select P2SB if X86
        select CHECK_SIGNATURE if X86 && DMI
        select I2C_SMBUS
        help

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index ff706349bdfb04d075d132afb9c69e25e07da352..f7a0bb372e8e4ebf4f1b39da9910b7fc19edf8b0 100644 (file)
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -111,6 +111,7 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/itco_wdt.h>
+#include <linux/platform_data/x86/p2sb.h>
 #include <linux/pm_runtime.h>
 #include <linux/mutex.h>
 
@@ -140,7 +141,6 @@
 #define TCOBASE                0x050
 #define TCOCTL         0x054
 
-#define SBREG_BAR              0x10
 #define SBREG_SMBCTRL          0xc6000c
 #define SBREG_SMBCTRL_DNV      0xcf000c
 
@@ -1482,45 +1482,24 @@ i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
                .version = 4,
        };
        struct resource *res;
-       unsigned int devfn;
-       u64 base64_addr;
-       u32 base_addr;
-       u8 hidden;
+       int ret;
 
        /*
         * We must access the NO_REBOOT bit over the Primary to Sideband
-        * bridge (P2SB). The BIOS prevents the P2SB device from being
-        * enumerated by the PCI subsystem, so we need to unhide/hide it
-        * to lookup the P2SB BAR.
+        * (P2SB) bridge.
         */
-       pci_lock_rescan_remove();
-
-       devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
-
-       /* Unhide the P2SB device, if it is hidden */
-       pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
-       if (hidden)
-               pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
-
-       pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
-       base64_addr = base_addr & 0xfffffff0;
-
-       pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
-       base64_addr |= (u64)base_addr << 32;
-
-       /* Hide the P2SB device, if it was hidden before */
-       if (hidden)
-               pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
-       pci_unlock_rescan_remove();
 
        res = &tco_res[1];
+       ret = p2sb_bar(pci_dev->bus, 0, res);
+       if (ret)
+               return ERR_PTR(ret);
+
        if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
-               res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
+               res->start += SBREG_SMBCTRL_DNV;
        else
-               res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
+               res->start += SBREG_SMBCTRL;
 
        res->end = res->start + 3;
-       res->flags = IORESOURCE_MEM;
 
        return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
                                        tco_res, 2, &pldata, sizeof(pldata));

diff --git a/drivers/platform/x86/intel/p2sb.c b/drivers/platform/x86/intel/p2sb.c
index b598ef14dbc67b678a87e5e100665e0ec2e4fb39..fb2e141f3eb84bd58916103feb4c7e81f85618a7 100644 (file)
--- a/drivers/platform/x86/intel/p2sb.c
+++ b/drivers/platform/x86/intel/p2sb.c
@@ -21,6 +21,12 @@
 
 static const struct x86_cpu_id p2sb_cpu_ids[] = {
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,       PCI_DEVFN(13, 0)),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,     PCI_DEVFN(31, 1)),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,   PCI_DEVFN(31, 1)),
+       X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,            PCI_DEVFN(31, 1)),
+       X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,          PCI_DEVFN(31, 1)),
+       X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,             PCI_DEVFN(31, 1)),
+       X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,           PCI_DEVFN(31, 1)),
        {}
 };