feat(imx8mq): enable dram dvfs support on imx8mq

Enable DRAM DVFS support on i.MX8MQ.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b

diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c
index a816c8073f96e46232fba8623212cc14d3041cde..6d6633cfcd901005901b63ce70fa642c14dfb874 100644 (file)
--- a/plat/imx/common/imx_sip_svc.c
+++ b/plat/imx/common/imx_sip_svc.c
@@ -36,6 +36,8 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
        case IMX_SIP_GPC:
                SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
                break;
+       case IMX_SIP_DDR_DVFS:
+               return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
 #endif
 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
        case IMX_SIP_DDR_DVFS:

diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h
index 1c319e8d8041e337da15159e784db8a5a447cd06..0e91c7174a52e8489c779ac6cdebea6e63de510f 100644 (file)
--- a/plat/imx/common/include/imx_sip_svc.h
+++ b/plat/imx/common/include/imx_sip_svc.h
@@ -57,6 +57,8 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
                         u_register_t x2, u_register_t x3);
 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
                    u_register_t x2, u_register_t x3);
+int dram_dvfs_handler(uint32_t smc_fid, void *handle,
+       u_register_t x1, u_register_t x2, u_register_t x3);
 #endif
 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
 int dram_dvfs_handler(uint32_t smc_fid, void *handle,

diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c
index 986ba6139c7d2dd35c556dbaaf0bc703f2762797..8b132d23114233e34883ff505909e13704a93e0e 100644 (file)
--- a/plat/imx/imx8m/ddr/clock.c
+++ b/plat/imx/imx8m/ddr/clock.c
@@ -76,7 +76,7 @@ void dram_pll_init(unsigned int drate)
 
        /* unbypass the PLL */
        mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30);
-       while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & (1 << 31))) {
+       while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & BIT(31))) {
                ;
        }
 }

diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c
index f5f9df7a48f672573631daeabc162d34d29466f0..b5f697334e9187b656c5ffe62e469cb21227c9ed 100644 (file)
--- a/plat/imx/imx8m/ddr/dram.c
+++ b/plat/imx/imx8m/ddr/dram.c
@@ -11,6 +11,7 @@
 #include <plat/common/platform.h>
 
 #include <dram.h>
+#include <gpc.h>
 
 #define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT                0x10
 #define IMX_SIP_DDR_DVFS_GET_FREQ_INFO         0x11
@@ -350,7 +351,13 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle,
                                plat_ic_raise_el3_sgi(0x8, i);
                        }
                }
-
+#if defined(PLAT_imx8mq)
+               for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++) {
+                       if (i != cpu_id && online_cores & (1 << (i * 8))) {
+                               imx_gpc_core_wake(1 << i);
+                       }
+               }
+#endif
                /* make sure all the core in WFE */
                online_cores &= ~(0x1 << (cpu_id * 8));
                while (1) {

diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h
index eb33abd6cc4702ed6be0e75b7e8f307717d31056..8eb3e06bca2412b8cfe9666e9f86da2733b1a54b 100644 (file)
--- a/plat/imx/imx8m/include/gpc.h
+++ b/plat/imx/imx8m/include/gpc.h
@@ -80,6 +80,7 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on);
 
 #if defined(PLAT_imx8mq)
 void imx_gpc_set_a53_core_awake(uint32_t core_id);
+void imx_gpc_core_wake(uint32_t cpumask);
 #endif
 
 #endif /*IMX8M_GPC_H */