parisc: Increase parisc_cache_flush_threshold setting

In testing the "Fix non-access data TLB cache flush faults" change,
I noticed a significant improvement in glibc build and check times.
This led me to investigate the parisc_cache_flush_threshold setting.
It determines when we switch from line flushing to whole cache flushing.

It turned out that the parisc_cache_flush_threshold setting on
mako and mako2 machines (PA8800 and PA8900 processors) was way too
small. Adjusting this setting provided almost a factor two improvement
in the glibc build and check time.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 59c2d079f17892aac7d8d0549533adfe62ba136f..81f36d6407f0cc82850c9fd45d8e7442aecb19ff 100644 (file)
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -388,7 +388,7 @@ void __init parisc_setup_cache_timing(void)
 {
        unsigned long rangetime, alltime;
        unsigned long size;
-       unsigned long threshold;
+       unsigned long threshold, threshold2;
 
        alltime = mfctl(16);
        flush_data_cache();
@@ -403,8 +403,20 @@ void __init parisc_setup_cache_timing(void)
                alltime, size, rangetime);
 
        threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
-       if (threshold > cache_info.dc_size)
-               threshold = cache_info.dc_size;
+
+       /*
+        * The threshold computed above isn't very reliable since the
+        * flush times depend greatly on the percentage of dirty lines
+        * in the flush range. Further, the whole cache time doesn't
+        * include the time to refill lines that aren't in the mm/vma
+        * being flushed. By timing glibc build and checks on mako cpus,
+        * the following formula seems to work reasonably well. The
+        * value from the timing calculation is too small, and increases
+        * build and check times by almost a factor two.
+        */
+       threshold2 = cache_info.dc_size * num_online_cpus();
+       if (threshold2 > threshold)
+               threshold = threshold2;
        if (threshold)
                parisc_cache_flush_threshold = threshold;
        printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",