drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polaris

Leads to improper dpm on older parts.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1353
Fixes: 9902d4bb2bab ("drm/amd/powerplay: optimize the mclk dpm policy settings")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 6d2f13dc900e45c8edd27b9e399e37c29e14935a..0b9083c9067a9332edddc6e383c0e1ae17898d00 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1717,18 +1717,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
        data->current_profile_setting.sclk_down_hyst = 100;
        data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
        data->current_profile_setting.bupdate_mclk = 1;
-       if (adev->gmc.vram_width == 256) {
-               data->current_profile_setting.mclk_up_hyst = 10;
-               data->current_profile_setting.mclk_down_hyst = 60;
-               data->current_profile_setting.mclk_activity = 25;
-       } else if (adev->gmc.vram_width == 128) {
-               data->current_profile_setting.mclk_up_hyst = 5;
-               data->current_profile_setting.mclk_down_hyst = 16;
-               data->current_profile_setting.mclk_activity = 20;
-       } else if (adev->gmc.vram_width == 64) {
-               data->current_profile_setting.mclk_up_hyst = 3;
-               data->current_profile_setting.mclk_down_hyst = 16;
-               data->current_profile_setting.mclk_activity = 20;
+       if (hwmgr->chip_id >= CHIP_POLARIS10) {
+               if (adev->gmc.vram_width == 256) {
+                       data->current_profile_setting.mclk_up_hyst = 10;
+                       data->current_profile_setting.mclk_down_hyst = 60;
+                       data->current_profile_setting.mclk_activity = 25;
+               } else if (adev->gmc.vram_width == 128) {
+                       data->current_profile_setting.mclk_up_hyst = 5;
+                       data->current_profile_setting.mclk_down_hyst = 16;
+                       data->current_profile_setting.mclk_activity = 20;
+               } else if (adev->gmc.vram_width == 64) {
+                       data->current_profile_setting.mclk_up_hyst = 3;
+                       data->current_profile_setting.mclk_down_hyst = 16;
+                       data->current_profile_setting.mclk_activity = 20;
+               }
+       } else {
+               data->current_profile_setting.mclk_up_hyst = 0;
+               data->current_profile_setting.mclk_down_hyst = 100;
+               data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
        }
        hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
        hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;