radeon: insert 10ms sleep in dce5_crtc_load_lut

Per at least one tester this is enough magic to recover the regression
introduced for some people (but not all) in

commit 046144a856af7551fc95f309a17cc07ec45803d2
Author: Peter Rosin <peda@axentia.se>
Date:   Tue Jul 4 12:36:57 2017 +0200

    drm/fb-helper: factor out pseudo-palette

which for radeon had the side-effect of refactoring out a seemingly
redudant writing of the color palette.

10ms in a fairly slow modeset path feels like an acceptable form of
duct-tape, so maybe worth a shot and see what sticks.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
References: https://bugzilla.kernel.org/show_bug.cgi?id=198123
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 856526cb2caf229820552a3fe4b2bcd3c309d3eb..82fa7ab6d35c9ceec0efa22b2a893e33f487498b 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -127,6 +127,8 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 
        DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 
+       msleep(10);
+
        WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
               (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
                NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));