drm/i915: Add windowing for primary planes on gen2/3 and chv

Plane B and C (note that we don't actually expose plane C currently)
on gen2/3 have a window generator, as does the primary plane on CHV
pipe B. So let's allow positioning of these planes freely within the
pipe source area.

Plane A on gen2/3 seems to have some kind of partial window generator
which would allow you to cut the plane off midway through the scanout,
but it would still have to start at the top-left corner of the pipe,
and it would have to be full width. That's doesn't sound all that
useful, so for simplicity let's just keep to the idea that plane A
has to be fullscreen.

Gen4 removed the plane A/B windowing support entirely, and it wasn't
reintroduced until SKL (apart from the CHV pipe B special case).

v2: s/plane/i9xx_plane/ etc. (James)
v3: Make it less confusing
v4: Deal with IS_GEN()

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190703200824.5971-2-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 919f5ac844c81a5dc54c6a183e7f553a31834bc6..1add3a0dfc06c943a18413565f13351a88223964 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3716,10 +3716,27 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
        return 0;
 }
 
+static bool i9xx_plane_has_windowing(struct intel_plane *plane)
+{
+       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+
+       if (IS_CHERRYVIEW(dev_priv))
+               return i9xx_plane == PLANE_B;
+       else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+               return false;
+       else if (IS_GEN(dev_priv, 4))
+               return i9xx_plane == PLANE_C;
+       else
+               return i9xx_plane == PLANE_B ||
+                       i9xx_plane == PLANE_C;
+}
+
 static int
 i9xx_plane_check(struct intel_crtc_state *crtc_state,
                 struct intel_plane_state *plane_state)
 {
+       struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
        int ret;
 
        ret = chv_plane_check_rotation(plane_state);
@@ -3730,7 +3747,8 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
                                                  &crtc_state->base,
                                                  DRM_PLANE_HELPER_NO_SCALING,
                                                  DRM_PLANE_HELPER_NO_SCALING,
-                                                 false, true);
+                                                 i9xx_plane_has_windowing(plane),
+                                                 true);
        if (ret)
                return ret;
 
@@ -3759,6 +3777,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
        u32 linear_offset;
        int x = plane_state->color_plane[0].x;
        int y = plane_state->color_plane[0].y;
+       int crtc_x = plane_state->base.dst.x1;
+       int crtc_y = plane_state->base.dst.y1;
+       int crtc_w = drm_rect_width(&plane_state->base.dst);
+       int crtc_h = drm_rect_height(&plane_state->base.dst);
        unsigned long irqflags;
        u32 dspaddr_offset;
        u32 dspcntr;
@@ -3777,18 +3799,18 @@ static void i9xx_update_plane(struct intel_plane *plane,
        I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
 
        if (INTEL_GEN(dev_priv) < 4) {
-               /* pipesrc and dspsize control the size that is scaled from,
-                * which should always be the user's requested size.
+               /*
+                * PLANE_A doesn't actually have a full window
+                * generator but let's assume we still need to
+                * program whatever is there.
                 */
-               I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
+               I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
                I915_WRITE_FW(DSPSIZE(i9xx_plane),
-                             ((crtc_state->pipe_src_h - 1) << 16) |
-                             (crtc_state->pipe_src_w - 1));
+                             ((crtc_h - 1) << 16) | (crtc_w - 1));
        } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
-               I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
+               I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
                I915_WRITE_FW(PRIMSIZE(i9xx_plane),
-                             ((crtc_state->pipe_src_h - 1) << 16) |
-                             (crtc_state->pipe_src_w - 1));
+                             ((crtc_h - 1) << 16) | (crtc_w - 1));
                I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
        }