amd/amdgpu: Limit rlcg write registers only for nv12

Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized
so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 04c5c8d257a3e48f73be948f620e2de8897f825f..38f704705dbc9bb645dfc953a261050547834026 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4577,11 +4577,13 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
        adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
 
        /* csib */
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
-                    adev->gfx.rlc.clear_state_gpu_addr >> 32);
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
-                    adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+       /* amdgpu_mm_wreg_mmio_rlc will fall back to mmio if doesn't support rlcg_write */
+       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
+                                adev->gfx.rlc.clear_state_gpu_addr >> 32, 0);
+       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
+                                adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc, 0);
+       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
+                                adev->gfx.rlc.clear_state_size, 0);
 
        return 0;
 }
@@ -5190,7 +5192,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
        tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
-       WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
+       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp, 0);
 
        for (i = 0; i < adev->usec_timeout; i++) {
                if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
@@ -7088,6 +7090,20 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
        .reset = gfx_v10_0_rlc_reset,
        .start = gfx_v10_0_rlc_start,
        .update_spm_vmid = gfx_v10_0_update_spm_vmid,
+};
+
+static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
+       .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
+       .set_safe_mode = gfx_v10_0_set_safe_mode,
+       .unset_safe_mode = gfx_v10_0_unset_safe_mode,
+       .init = gfx_v10_0_rlc_init,
+       .get_csb_size = gfx_v10_0_get_csb_size,
+       .get_csb_buffer = gfx_v10_0_get_csb_buffer,
+       .resume = gfx_v10_0_rlc_resume,
+       .stop = gfx_v10_0_rlc_stop,
+       .reset = gfx_v10_0_rlc_reset,
+       .start = gfx_v10_0_rlc_start,
+       .update_spm_vmid = gfx_v10_0_update_spm_vmid,
        .rlcg_wreg = gfx_v10_rlcg_wreg,
        .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
 };
@@ -8185,9 +8201,11 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_NAVI10:
        case CHIP_NAVI14:
-       case CHIP_NAVI12:
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                break;
+       case CHIP_NAVI12:
+               adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
+               break;
        default:
                break;
        }