clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT

Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 7ef7963126b67c0c4dd7f51f095e9bd2b46e862f..d3c3469d47d984f531db05b2017c2219ec78d369 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -117,7 +117,8 @@ static const struct {
                  .p = "cpupll_fracck",
                  .l = &pll_layout_divpmc,
                  .t = PLL_TYPE_DIV,
-                 .c = 1, },
+                 .c = 1,
+                 .eid = PMC_CPUPLL, },
        },
 
        [PLL_ID_SYS] = {
@@ -131,7 +132,8 @@ static const struct {
                  .p = "syspll_fracck",
                  .l = &pll_layout_divpmc,
                  .t = PLL_TYPE_DIV,
-                 .c = 1, },
+                 .c = 1,
+                 .eid = PMC_SYSPLL, },
        },
 
        [PLL_ID_DDR] = {