drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845

The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it.

This also adds separate feature bits for INTF (based on downstream) instead
of using CTL feature bit for it, and removes the unnecessary NULL check in
the added bind_pingpong_blk function.

Fixes: 61e62905a96a53bb5eb6f38164cab ("msm:disp:dpu1: setup display datapath for SC7180 target")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c30b3087f887d3809207da391c44123e29b75cf7..922cdb494fb6b7ad8bbc5eceb874ce7bd8a196c6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -43,6 +43,10 @@
 
 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
 
+#define INTF_SDM845_MASK (0)
+
+#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
+
 #define DEFAULT_PIXEL_RAM_SIZE         (50 * 1024)
 #define DEFAULT_DPU_LINE_WIDTH         2048
 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH  2560
@@ -398,26 +402,26 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
 /*************************************************************
  * INTF sub blocks config
  *************************************************************/
-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \
+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \
        {\
        .name = _name, .id = _id, \
        .base = _base, .len = 0x280, \
-       .features = BIT(DPU_CTL_ACTIVE_CFG), \
+       .features = _features, \
        .type = _type, \
        .controller_id = _ctrl_id, \
        .prog_fetch_lines_worst_case = 24 \
        }
 
 static const struct dpu_intf_cfg sdm845_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
-       INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
-       INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1),
-       INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
+       INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK),
+       INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK),
+       INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK),
+       INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK),
 };
 
 static const struct dpu_intf_cfg sc7180_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
-       INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
+       INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
+       INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
 };
 
 /*************************************************************

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index a6221fdc02d20958f21ce0ece25ac0c2bbdc7da0..e9458c85e20cfb1b9ee8177db7132ed787d1356d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -186,6 +186,19 @@ enum {
        DPU_CTL_MAX
 };
 
+/**
+ * INTF sub-blocks
+ * @DPU_INTF_INPUT_CTRL         Supports the setting of pp block from which
+ *                              pixel data arrives to this INTF
+ * @DPU_INTF_TE                 INTF block has TE configuration support
+ * @DPU_INTF_MAX
+ */
+enum {
+       DPU_INTF_INPUT_CTRL = 0x1,
+       DPU_INTF_TE,
+       DPU_INTF_MAX
+};
+
 /**
  * VBIF sub-blocks and features
  * @DPU_VBIF_QOS_OTLIM        VBIF supports OT Limit

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index efe9a5719c6b76c55b8a573ebddc8b5e4e0ff5ea..64f556d693dda150ee983e48e76d73181a23f4b7 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -225,14 +225,9 @@ static void dpu_hw_intf_bind_pingpong_blk(
                bool enable,
                const enum dpu_pingpong pp)
 {
-       struct dpu_hw_blk_reg_map *c;
+       struct dpu_hw_blk_reg_map *c = &intf->hw;
        u32 mux_cfg;
 
-       if (!intf)
-               return;
-
-       c = &intf->hw;
-
        mux_cfg = DPU_REG_READ(c, INTF_MUX);
        mux_cfg &= ~0xf;
 
@@ -280,7 +275,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
        ops->get_status = dpu_hw_intf_get_status;
        ops->enable_timing = dpu_hw_intf_enable_timing_engine;
        ops->get_line_count = dpu_hw_intf_get_line_count;
-       if (cap & BIT(DPU_CTL_ACTIVE_CFG))
+       if (cap & BIT(DPU_INTF_INPUT_CTRL))
                ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
 }