#define CONFIG_SYS_NAND_FTIM3 0x0
#endif
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#endif
/* USB Configs */
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { \
24, 25, 26, 27, 28, \
29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { \
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ECCSTEPS 4
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
-
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/*
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE