/* Chip-specific data and limits */
#define RTL8365MB_CHIP_ID_8365MB_VC 0x6367
-#define RTL8365MB_CPU_PORT_NUM_8365MB_VC 6
#define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112
static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1 };
#define RTL8365MB_PHYADDRMAX 7
#define RTL8365MB_NUM_PHYREGS 32
#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
-#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
+#define RTL8365MB_MAX_NUM_PORTS 7
/* Chip identification registers */
#define RTL8365MB_CHIP_ID_REG 0x1300
static int rtl8365mb_setup(struct dsa_switch *ds)
{
struct realtek_priv *priv = ds->priv;
+ struct dsa_port *cpu_dp;
struct rtl8365mb *mb;
int ret;
int i;
dev_info(priv->dev, "no interrupt support\n");
/* Configure CPU tagging */
- ret = rtl8365mb_cpu_config(priv);
- if (ret)
- goto out_teardown_irq;
+ /* Currently, only one CPU port is supported */
+ dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {
+ priv->cpu_port = cpu_dp->index;
+ mb->cpu.mask = BIT(priv->cpu_port);
+ mb->cpu.trap_port = priv->cpu_port;
+ ret = rtl8365mb_cpu_config(priv);
+ if (ret)
+ goto out_teardown_irq;
+
+ break;
+ }
/* Configure ports */
for (i = 0; i < priv->num_ports; i++) {
"found an RTL8365MB-VC switch (ver=0x%04x)\n",
chip_ver);
- priv->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC;
- priv->num_ports = priv->cpu_port + 1;
+ priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
mb->priv = priv;
mb->chip_id = chip_id;
mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc);
mb->cpu.enable = 1;
- mb->cpu.mask = BIT(priv->cpu_port);
- mb->cpu.trap_port = priv->cpu_port;
mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;