fix(intel): mailbox store QSPI ref clk in scratch reg

When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff

diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 7f6731307f2ce565b929e602fccb7f3e8d031009..69ee6d3e9b0d76b573367cd73a71f7dc779e1c70 100644 (file)
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -42,6 +42,8 @@
 #define IDLE_DATA_SOC2FPGA                             BIT(0)
 #define IDLE_DATA_MASK         (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
 
+#define SYSMGR_QSPI_REFCLK_MASK                                GENMASK(27, 0)
+
 #define SYSMGR_ECC_OCRAM_MASK                          BIT(1)
 #define SYSMGR_ECC_DDR0_MASK                           BIT(16)
 #define SYSMGR_ECC_DDR1_MASK                           BIT(17)

diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 79817e64c5de3db0c5307769c8d5b9cbb7a4c59f..e19364690ee46cd42655bee8a07756156572da82 100644 (file)
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -10,6 +10,7 @@
 
 #include "socfpga_mailbox.h"
 #include "socfpga_sip_svc.h"
+#include "socfpga_system_manager.h"
 
 static mailbox_payload_t mailbox_resp_payload;
 static mailbox_container_t mailbox_resp_ctr = {0, 0, &mailbox_resp_payload};
@@ -464,8 +465,26 @@ void mailbox_set_qspi_open(void)
 
 void mailbox_set_qspi_direct(void)
 {
+       uint32_t response[1], qspi_clk, reg;
+       unsigned int resp_len = ARRAY_SIZE(response);
+
        mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U,
-                               CMD_CASUAL, NULL, NULL);
+                        CMD_CASUAL, response, &resp_len);
+
+       qspi_clk = response[0];
+       INFO("QSPI ref clock: %u\n", qspi_clk);
+
+       /*
+        * Store QSPI ref clock frequency in BOOT_SCRATCH_COLD_0 register for
+        * later boot loader (i.e. u-boot) use.
+        * The frequency is stored in kHz and occupies BOOT_SCRATCH_COLD_0
+        * register bits[27:0].
+        */
+       qspi_clk /= 1000;
+       reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0));
+       reg &= ~SYSMGR_QSPI_REFCLK_MASK;
+       reg |= qspi_clk & SYSMGR_QSPI_REFCLK_MASK;
+       mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0), reg);
 }
 
 void mailbox_set_qspi_close(void)