fix(pmu): add sensible default for MDCR_EL2

When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 is poorly defined when FEAT_HPMN0 is not implemented.
Set it to its hardware reset value so that lower ELs don't inherit a
wrong value.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8055005ef9b6eaafefa13b62a0b41289079fdd23

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 8213cbe88ebb322fa7234046f7c394ec638c844d..8b45c642255583fb69a4cedf5944a64a76302394 100644 (file)
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -249,6 +249,16 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
                                   ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
        write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
                        icc_sre_el2);
+
+       /*
+        * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't
+        * throw anyone off who expects this to be sensible.
+        * TODO: A similar thing happens in cm_prepare_el3_exit. They should be
+        * unified with the proper PMU implementation
+        */
+       u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) &
+                       PMCR_EL0_N_MASK);
+       write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2);
 #endif /* CTX_INCLUDE_EL2_REGS */
 }