ALSA: hda: Clear RIRB status before reading WP

RIRB interrupt status getting cleared after the write pointer is read
causes a race condition, where last response(s) into RIRB may remain
unserviced by IRQ, eventually causing azx_rirb_get_response to fall
back to polling mode. Clearing the RIRB interrupt status ahead of
write pointer access ensures that this condition is avoided.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Link: https://lore.kernel.org/r/1580983853-351-1-git-send-email-viswanathl@nvidia.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>

diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
index 9757667cdd582eb061907d09b435c2d88b23115b..2609e391ce54967eb3e2fd4d1fca2a43f6ea821f 100644 (file)
--- a/sound/pci/hda/hda_controller.c
+++ b/sound/pci/hda/hda_controller.c
@@ -1110,16 +1110,23 @@ irqreturn_t azx_interrupt(int irq, void *dev_id)
                if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
                        active = true;
 
-               /* clear rirb int */
                status = azx_readb(chip, RIRBSTS);
                if (status & RIRB_INT_MASK) {
+                       /*
+                        * Clearing the interrupt status here ensures that no
+                        * interrupt gets masked after the RIRB wp is read in
+                        * snd_hdac_bus_update_rirb. This avoids a possible
+                        * race condition where codec response in RIRB may
+                        * remain unserviced by IRQ, eventually falling back
+                        * to polling mode in azx_rirb_get_response.
+                        */
+                       azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
                        active = true;
                        if (status & RIRB_INT_RESPONSE) {
                                if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
                                        udelay(80);
                                snd_hdac_bus_update_rirb(bus);
                        }
-                       azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
                }
        } while (active && ++repeat < 10);