dt-bindings: clock: Add and reorder ABI for X1000.

1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
  directly derived from the output of SSIPLL, but from the clock
  obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
  is added for this purpose, it must between "X1000_CLK_SSIPLL"
  and "X1000_CLK_SSIMUX", otherwise an error will occurs when
  initializing the clock. These ABIs are only used for X1000, and
  I'm sure that no other devicetree out there is using these ABIs,
  so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200528031549.13846-7-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
index bbaebaf7adb90892eb73d7c63f2616ae1a3b97c9..0367c8c02e16e5a60e2ffd042b8e14c0a51187a0 100644 (file)
--- a/include/dt-bindings/clock/x1000-cgu.h
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -12,33 +12,41 @@
 #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
 #define __DT_BINDINGS_CLOCK_X1000_CGU_H__
 
-#define X1000_CLK_EXCLK                0
-#define X1000_CLK_RTCLK                1
-#define X1000_CLK_APLL         2
-#define X1000_CLK_MPLL         3
-#define X1000_CLK_SCLKA                4
-#define X1000_CLK_CPUMUX       5
-#define X1000_CLK_CPU          6
-#define X1000_CLK_L2CACHE      7
-#define X1000_CLK_AHB0         8
-#define X1000_CLK_AHB2PMUX     9
-#define X1000_CLK_AHB2         10
-#define X1000_CLK_PCLK         11
-#define X1000_CLK_DDR          12
-#define X1000_CLK_MAC          13
-#define X1000_CLK_MSCMUX       14
-#define X1000_CLK_MSC0         15
-#define X1000_CLK_MSC1         16
-#define X1000_CLK_SSIPLL       17
-#define X1000_CLK_SSIMUX       18
-#define X1000_CLK_SFC          19
-#define X1000_CLK_I2C0         20
-#define X1000_CLK_I2C1         21
-#define X1000_CLK_I2C2         22
-#define X1000_CLK_UART0                23
-#define X1000_CLK_UART1                24
-#define X1000_CLK_UART2                25
-#define X1000_CLK_SSI          26
-#define X1000_CLK_PDMA         27
+#define X1000_CLK_EXCLK                        0
+#define X1000_CLK_RTCLK                        1
+#define X1000_CLK_APLL                 2
+#define X1000_CLK_MPLL                 3
+#define X1000_CLK_OTGPHY               4
+#define X1000_CLK_SCLKA                        5
+#define X1000_CLK_CPUMUX               6
+#define X1000_CLK_CPU                  7
+#define X1000_CLK_L2CACHE              8
+#define X1000_CLK_AHB0                 9
+#define X1000_CLK_AHB2PMUX             10
+#define X1000_CLK_AHB2                 11
+#define X1000_CLK_PCLK                 12
+#define X1000_CLK_DDR                  13
+#define X1000_CLK_MAC                  14
+#define X1000_CLK_LCD                  15
+#define X1000_CLK_MSCMUX               16
+#define X1000_CLK_MSC0                 17
+#define X1000_CLK_MSC1                 18
+#define X1000_CLK_OTG                  19
+#define X1000_CLK_SSIPLL               20
+#define X1000_CLK_SSIPLL_DIV2  21
+#define X1000_CLK_SSIMUX               22
+#define X1000_CLK_EMC                  23
+#define X1000_CLK_EFUSE                        24
+#define X1000_CLK_SFC                  25
+#define X1000_CLK_I2C0                 26
+#define X1000_CLK_I2C1                 27
+#define X1000_CLK_I2C2                 28
+#define X1000_CLK_UART0                        29
+#define X1000_CLK_UART1                        30
+#define X1000_CLK_UART2                        31
+#define X1000_CLK_TCU                  32
+#define X1000_CLK_SSI                  33
+#define X1000_CLK_OST                  34
+#define X1000_CLK_PDMA                 35
 
 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */