drm/i915/uc: Unify uC platform check

We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace all the checks with a unified
HAS_UC.

v2: use HAS_GT_UC (Michal)
v3: fix comment (Michal)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190725001813.4740-2-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 55e2ddcbd2158ce192298fac982d92eb64315ab6..98c071fe532bf82433d3c24fa605437cae307d97 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -595,7 +595,7 @@ int intel_reset_guc(struct intel_gt *gt)
                INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
        int ret;
 
-       GEM_BUG_ON(!HAS_GUC(gt->i915));
+       GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 
        intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
        ret = gen6_hw_domain_reset(gt, guc_domain);

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3dfa40fdbe997b5fa05085cf1c84d0d709e01235..87169e8267475c6c28ee9ecf9cff2b28b94f691f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -80,7 +80,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
 
        GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
-       if (!HAS_GUC(i915)) {
+       if (!HAS_GT_UC(i915)) {
                guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
                return;
        }

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 543854c42d9dc8c81ac06d8bd74e97e4f1a225a9..ff6f7b157ecba5ad0d1c18f918cb03e22aa947eb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -74,7 +74,7 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
 
        GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 
-       if (!HAS_HUC(dev_priv)) {
+       if (!HAS_GT_UC(dev_priv)) {
                huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
                return;
        }

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 25a8ab3bd22cce4bd987916bf485be98376781b5..bdb171c3f36e31060e85439d9667e9c5f38733b2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -61,7 +61,7 @@ static int __get_platform_enable_guc(struct intel_uc *uc)
        struct intel_uc_fw *huc_fw = &uc->huc.fw;
        int enable_guc = 0;
 
-       if (!HAS_GUC(uc_to_gt(uc)->i915))
+       if (!HAS_GT_UC(uc_to_gt(uc)->i915))
                return 0;
 
        /* We don't want to enable GuC/HuC on pre-Gen11 by default */

diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index 93f7c930ab181f6d84e809fc98922504dd5ce442..371f7a60c98738321ede2182763a836078282220 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -134,7 +134,7 @@ static int igt_guc_clients(void *args)
        struct intel_guc *guc;
        int err = 0;
 
-       GEM_BUG_ON(!HAS_GUC(dev_priv));
+       GEM_BUG_ON(!HAS_GT_UC(dev_priv));
        mutex_lock(&dev_priv->drm.struct_mutex);
        wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
@@ -226,7 +226,7 @@ static int igt_guc_doorbells(void *arg)
        int i, err = 0;
        u16 db_id;
 
-       GEM_BUG_ON(!HAS_GUC(dev_priv));
+       GEM_BUG_ON(!HAS_GT_UC(dev_priv));
        mutex_lock(&dev_priv->drm.struct_mutex);
        wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d3911469801b175f87efebadd49bf7de5bc73e8..24787bb48c9fb6a88008917a0bfd3212157d7f38 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1865,7 +1865,7 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
        intel_wakeref_t wakeref;
        struct drm_printer p;
 
-       if (!HAS_HUC(dev_priv))
+       if (!HAS_GT_UC(dev_priv))
                return -ENODEV;
 
        p = drm_seq_file_printer(m);
@@ -1883,7 +1883,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
        intel_wakeref_t wakeref;
        struct drm_printer p;
 
-       if (!HAS_GUC(dev_priv))
+       if (!HAS_GT_UC(dev_priv))
                return -ENODEV;
 
        p = drm_seq_file_printer(m);
@@ -2062,7 +2062,7 @@ static int i915_guc_log_dump(struct seq_file *m, void *data)
        u32 *log;
        int i = 0;
 
-       if (!HAS_GUC(dev_priv))
+       if (!HAS_GT_UC(dev_priv))
                return -ENODEV;
 
        if (dump_load_err)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a58fb8c88c280d831585767c8b15eba337e9620..364a9fb543b6508ef0b962640a1bc65427bd3433 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2271,20 +2271,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPC(dev_priv)               (INTEL_INFO(dev_priv)->display.has_ipc)
 
-/*
- * For now, anything with a GuC requires uCode loading, and then supports
- * command submission once loaded. But these are logically independent
- * properties, so we have separate macros to test them.
- */
-#define HAS_GUC(dev_priv)      (INTEL_INFO(dev_priv)->has_guc)
-#define HAS_GUC_UCODE(dev_priv)        (HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)        (HAS_GUC(dev_priv))
-
-/* For now, anything with a GuC has also HuC */
-#define HAS_HUC(dev_priv)      (HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)        (HAS_GUC(dev_priv))
+#define HAS_GT_UC(dev_priv)    (INTEL_INFO(dev_priv)->has_gt_uc)
 
-/* Having a GuC is not the same as using a GuC */
+/* Having GuC/HuC is not the same as using GuC/HuC */
 #define USES_GUC(dev_priv)             intel_uc_is_using_guc(&(dev_priv)->gt.uc)
 #define USES_GUC_SUBMISSION(dev_priv)  intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
 #define USES_HUC(dev_priv)             intel_uc_is_using_huc(&(dev_priv)->gt.uc)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2193687eac72aa57abca9442111880189dfbabf1..56dfc2650836a31b16dc75b033f36aca02928fa5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -651,7 +651,7 @@ static void err_print_uc(struct drm_i915_error_state_buf *m,
        const struct i915_gpu_state *error =
                container_of(error_uc, typeof(*error), uc);
 
-       if (!error->device_info.has_guc)
+       if (!error->device_info.has_gt_uc)
                return;
 
        intel_uc_fw_dump(&error_uc->guc_fw, &p);
@@ -1455,7 +1455,7 @@ capture_uc_state(struct i915_gpu_state *error, struct compress *compress)
        struct intel_uc *uc = &i915->gt.uc;
 
        /* Capturing uC state won't be useful if there is no GuC */
-       if (!error->device_info.has_guc)
+       if (!error->device_info.has_gt_uc)
                return;
 
        error_uc->guc_fw = uc->guc.fw;

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 11c73af92597d85b27ed7e99d2905ebfe871eb9c..a17d4fd179621bb6d4417ecfb6e5252c0d518372 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4766,7 +4766,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                dev_priv->l3_parity.remap_info[i] = NULL;
 
        /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
-       if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
+       if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
                dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
 
        /* Let's track the enabled rps events */

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 40076ba431d45328b7bc1f6e87410f88322e6fac..bd9211b3d76e90c0efb7ff868d32297162cf4f8d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,7 +595,7 @@ static const struct intel_device_info intel_cherryview_info = {
        GEN9_DEFAULT_PAGE_SIZES, \
        .has_logical_ring_preemption = 1, \
        .display.has_csr = 1, \
-       .has_guc = 1, \
+       .has_gt_uc = 1, \
        .display.has_ipc = 1, \
        .ddb_size = 896
 
@@ -647,7 +647,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
        .display.has_dp_mst = 1, \
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_preemption = 1, \
-       .has_guc = 1, \
+       .has_gt_uc = 1, \
        .ppgtt_type = INTEL_PPGTT_FULL, \
        .ppgtt_size = 48, \
        .has_reset_engine = 1, \

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 45a9badc9b8e1c3e1e2d8f662397251d1cc2ac75..4f58e8d71b67a8d6b53dbb2499504ada08fbc286 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,7 +112,7 @@ enum intel_ppgtt_type {
        func(gpu_reset_clobbers_display); \
        func(has_reset_engine); \
        func(has_fpga_dbg); \
-       func(has_guc); \
+       func(has_gt_uc); \
        func(has_l3_dpf); \
        func(has_llc); \
        func(has_logical_ring_contexts); \

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22472f2bd31b76dd9124c075cda183a75295557a..30399b245f07f42930e8496ce3350c7fa7c93720 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7162,7 +7162,7 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
        for_each_engine(engine, dev_priv, id)
                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
 
-       if (HAS_GUC(dev_priv))
+       if (HAS_GT_UC(dev_priv))
                I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
 
        I915_WRITE(GEN6_RC_SLEEP, 0);
@@ -7243,7 +7243,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
        for_each_engine(engine, dev_priv, id)
                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
 
-       if (HAS_GUC(dev_priv))
+       if (HAS_GT_UC(dev_priv))
                I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
 
        I915_WRITE(GEN6_RC_SLEEP, 0);

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index fafd4e6a11473a2a6fa42abb522bc19abea2dd40..0e86a9e85b4969077ad26d5bc4ffe250b1746f38 100644 (file)
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -74,7 +74,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
 {
        struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
 
-       if (!HAS_GUC(i915))
+       if (!HAS_GT_UC(i915))
                return;
 
        if (INTEL_GEN(i915) >= 11)
@@ -263,7 +263,7 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
        if (!USES_GUC(i915))
                return 0;
 
-       GEM_BUG_ON(!HAS_GUC(i915));
+       GEM_BUG_ON(!HAS_GT_UC(i915));
        GEM_BUG_ON(!wopcm->guc.size);
        GEM_BUG_ON(!wopcm->guc.base);