OMAP5912: fix FIFO handling in UART driver

According to the OMAP5912 Serial Interfaces Reference Guide (see
http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the
FIFO_EN enable bit in the FIFO Control Register (FCR) can only be
changed when the baud clock is not running, i. e. when both DLL and
DLH are set to 0.

Thus make sure that DLL and DLH are 0 when writing the FCR.

Signed-off-by: Wolfgang Denk <wd@denx.de>

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 2429464d89656f167480ba0efc4af7fb4584adf0..6b3f60eb575c3d9eaf31f92da5a169a58167e677 100644 (file)
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -21,11 +21,15 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
        com_port->mdr1 = 0x7;   /* mode select reset TL16C750*/
 #endif
        com_port->lcr = LCR_BKSE | LCRVAL;
-       com_port->dll = baud_divisor & 0xff;
-       com_port->dlm = (baud_divisor >> 8) & 0xff;
+       com_port->dll = 0;
+       com_port->dlm = 0;
        com_port->lcr = LCRVAL;
        com_port->mcr = MCRVAL;
        com_port->fcr = FCRVAL;
+       com_port->lcr = LCR_BKSE | LCRVAL;
+       com_port->dll = baud_divisor & 0xff;
+       com_port->dlm = (baud_divisor >> 8) & 0xff;
+       com_port->lcr = LCRVAL;
 #if defined(CONFIG_OMAP)
 #if defined(CONFIG_APTIX)
        com_port->mdr1 = 3;     /* /13 mode so Aptix 6MHz can hit 115200 */
@@ -38,12 +42,16 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
        com_port->ier = 0x00;
+       com_port->lcr = LCR_BKSE | LCRVAL;
+       com_port->dll = 0;
+       com_port->dlm = 0;
+       com_port->lcr = LCRVAL;
+       com_port->mcr = MCRVAL;
+       com_port->fcr = FCRVAL;
        com_port->lcr = LCR_BKSE;
        com_port->dll = baud_divisor & 0xff;
        com_port->dlm = (baud_divisor >> 8) & 0xff;
        com_port->lcr = LCRVAL;
-       com_port->mcr = MCRVAL;
-       com_port->fcr = FCRVAL;
 }
 
 void NS16550_putc (NS16550_t com_port, char c)