drm/i915/gvt: addressed guest GPU hang with HWS index mode

with the introduce of "switch to use HWS indices rather than address",
guest GPU hang observed when running workloads which will update the
seqno to the real HW HWSP, not vitural GPU HWSP and then cause GPU hang.

this patch is to revoke index mode in PIPE_CTRL and MI_FLUSH_DW and
patch guest GPU HWSP address value to these commands.

Fixes: e2f46c32f876 ("drm/i915: Switch to use HWS indices rather than addresses")
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 57a92a86c63e2c8c20255cac9137b0d892cc1458..5a767180e430bf990a8fba1079d07d218f594d6d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1077,6 +1077,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
        bool index_mode = false;
        unsigned int post_sync;
        int ret = 0;
+       u32 hws_pga, val;
 
        post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
 
@@ -1100,6 +1101,15 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
                                        index_mode = true;
                                ret |= cmd_address_audit(s, gma, sizeof(u64),
                                                index_mode);
+                               if (ret)
+                                       return ret;
+                               if (index_mode) {
+                                       hws_pga = s->vgpu->hws_pga[s->ring_id];
+                                       gma = hws_pga + gma;
+                                       patch_value(s, cmd_ptr(s, 2), gma);
+                                       val = cmd_val(s, 1) & (~(1 << 21));
+                                       patch_value(s, cmd_ptr(s, 1), val);
+                               }
                        }
                }
        }
@@ -1569,6 +1579,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
        unsigned long gma;
        bool index_mode = false;
        int ret = 0;
+       u32 hws_pga, val;
 
        /* Check post-sync and ppgtt bit */
        if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
@@ -1579,6 +1590,15 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
                if (cmd_val(s, 0) & (1 << 21))
                        index_mode = true;
                ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
+               if (ret)
+                       return ret;
+               if (index_mode) {
+                       hws_pga = s->vgpu->hws_pga[s->ring_id];
+                       gma = hws_pga + gma;
+                       patch_value(s, cmd_ptr(s, 1), gma);
+                       val = cmd_val(s, 0) & (~(1 << 21));
+                       patch_value(s, cmd_ptr(s, 0), val);
+               }
        }
        /* Check notify bit */
        if ((cmd_val(s, 0) & (1 << 8)))