mmc: rockchip_dw_mmc: Fix get_mmc_clk return value

The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.

The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.

Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 3661ce33143ea096428ba6461ed910ed2244ed3e..72c820ee63308ae7999df94acb7012d13699cbb3 100644 (file)
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
        ret = clk_set_rate(&priv->clk, freq);
        if (ret < 0) {
                debug("%s: err=%d\n", __func__, ret);
-               return ret;
+               return 0;
        }
 
        return freq;