Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx...

* clk-hisi:
  clk: hi6220: use CLK_OF_DECLARE_DRIVER

* clk-amlogic:
  clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
  clk: meson: axg_audio: add sm1 support
  clk: meson: axg-audio: provide clk top signal name
  clk: meson: axg-audio: prepare sm1 addition
  clk: meson: axg-audio: fix regmap last register
  clk: meson: axg-audio: remove useless defines
  dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  dt-bindings: clk: axg-audio: add sm1 bindings
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

* clk-samsung:
  clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
  clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
  clk: samsung: exynos5420: Add VPLL rate table
  clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
  clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
  clk: samsung: exynos5433: Fix error paths

* clk-renesas: (23 commits)
  clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
  clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
  dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
  clk: renesas: r8a77965: Remove superfluous semicolon
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
  dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
  clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
  clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
  clk: renesas: r8a774b1: Add TMU clock
  clk: renesas: cpg-mssr: Add r8a774b1 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
  clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
  clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
  clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
  clk: renesas: rcar-gen3: Improve arithmetic divisions
  clk: renesas: rcar-gen2: Improve arithmetic divisions
  clk: renesas: Remove R-Car Gen2 legacy DT clock support
  ...

* clk-imx:
  clk: imx: imx8mq: fix sys3_pll_out_sels
  clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
  clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx7ulp: Correct DDR clock mux options
  clk: imx7ulp: Correct system clock source option #7
  clk: imx: imx8mq: mark sys1/2_pll as fixed clock
  clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
  clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
  clk: imx8mn: Define gates for pll1/2 fixed dividers
  clk: imx8mm: Define gates for pll1/2 fixed dividers
  clk: imx8mq: Define gates for pll1/2 fixed dividers
  clk: imx: clk-pll14xx: Make two variables static
  clk: imx8mq: Add VIDEO2_PLL clock
  clk: imx8mn: Use common 1443X/1416X PLL clock structure
  clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
  clk: imx: pll14xx: Fix quick switch of S/K parameter

diff --cc drivers/clk/imx/clk-imx8mn.c
index ccd05321f043fa5bc91dba35c53075a374819c72,47a4b44ba3cb00319297e5afa2ec1490c50481be,47a4b44ba3cb00319297e5afa2ec1490c50481be,47a4b44ba3cb00319297e5afa2ec1490c50481be,47a4b44ba3cb00319297e5afa2ec1490c50481be,def10a4da6036949db028fd0579b7fb6b340aad6..ecf044013a0143db61f4abf2b2435b24a846fa78
--- 1/drivers/clk/imx/clk-imx8mn.c
--- 2/drivers/clk/imx/clk-imx8mn.c
--- 3/drivers/clk/imx/clk-imx8mn.c
--- 4/drivers/clk/imx/clk-imx8mn.c
--- 5/drivers/clk/imx/clk-imx8mn.c
--- 6/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@@@@@@ -25,75 -25,89 -25,89 -25,89 -25,89 -25,20 +25,6 @@@@@@@ static u32 share_count_disp
      static u32 share_count_pdm;
      static u32 share_count_nand;
      
 -----enum {
 -----  ARM_PLL,
 -----  GPU_PLL,
 -----  VPU_PLL,
 -----  SYS_PLL1,
 -----  SYS_PLL2,
 -----  SYS_PLL3,
 -----  DRAM_PLL,
 -----  AUDIO_PLL1,
 -----  AUDIO_PLL2,
 -----  VIDEO_PLL2,
 -----  NR_PLLS,
 ---- };
 ---- 
----- static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
-----   PLL_1416X_RATE(1800000000U, 225, 3, 0),
-----   PLL_1416X_RATE(1600000000U, 200, 3, 0),
-----   PLL_1416X_RATE(1500000000U, 375, 3, 1),
-----   PLL_1416X_RATE(1400000000U, 350, 3, 1),
-----   PLL_1416X_RATE(1200000000U, 300, 3, 1),
-----   PLL_1416X_RATE(1000000000U, 250, 3, 1),
-----   PLL_1416X_RATE(800000000U,  200, 3, 1),
-----   PLL_1416X_RATE(750000000U,  250, 2, 2),
-----   PLL_1416X_RATE(700000000U,  350, 3, 2),
-----   PLL_1416X_RATE(600000000U,  300, 3, 2),
----- };
----- 
----- static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
-----   PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
-----   PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
----- };
----- 
----- static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
-----   PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
-----   PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
----- };
----- 
----- static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
-----   PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_audio_pll = {
-----           .type = PLL_1443X,
-----           .rate_table = imx8mn_audiopll_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_video_pll = {
-----           .type = PLL_1443X,
-----           .rate_table = imx8mn_videopll_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_dram_pll = {
-----           .type = PLL_1443X,
-----           .rate_table = imx8mn_drampll_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_arm_pll = {
-----           .type = PLL_1416X,
-----           .rate_table = imx8mn_pll1416x_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_gpu_pll = {
-----           .type = PLL_1416X,
-----           .rate_table = imx8mn_pll1416x_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_vpu_pll = {
-----           .type = PLL_1416X,
-----           .rate_table = imx8mn_pll1416x_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
----- };
----- 
----- static struct imx_pll14xx_clk imx8mn_sys_pll = {
-----           .type = PLL_1416X,
-----           .rate_table = imx8mn_pll1416x_tbl,
-----           .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
------};
------
      static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
      static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
      static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };