bnxt_en: Fix bnxt_refclk_read()

The upper 32-bit PHC register is not latched when reading the lower
32-bit PHC register.  Current code leaves a small window where we may
not read correct higher order bits if the lower order bits are just about
to wrap around.

This patch fixes this by reading higher order bits twice and makes
sure that final value is correctly paired with its lower 32 bits.

Fixes: bd0bd5797b78 ("bnxt_en: Do not read the PTP PHC during chip reset")
Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
index 562f8f68a47d8b187c93ba10ad7e99212f3fc2b3..7f3c0875b6f5834e58223a13c3cfb1d46b02cec4 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
@@ -76,14 +76,23 @@ static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
                            u64 *ns)
 {
        struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
+       u32 high_before, high_now, low;
 
        if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
                return -EIO;
 
+       high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
        ptp_read_system_prets(sts);
-       *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
+       low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
        ptp_read_system_postts(sts);
-       *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32;
+       high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
+       if (high_now != high_before) {
+               ptp_read_system_prets(sts);
+               low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
+               ptp_read_system_postts(sts);
+       }
+       *ns = ((u64)high_now << 32) | low;
+
        return 0;
 }